公开(公告)号：US11302684B2

公开(公告)日：2022-04-12

申请号：US16783830

申请日：2020-02-06

Applicant: KIOXIA CORPORATION

Inventor： Jun Iijima ,  Yumi Nakajima

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

公开(公告)号：US12272676B2

公开(公告)日：2025-04-08

申请号：US18486194

申请日：2023-10-13

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US12089409B2

公开(公告)日：2024-09-10

申请号：US18339526

申请日：2023-06-22

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/04 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05095 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US11817428B2

公开(公告)日：2023-11-14

申请号：US17590373

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/50 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US11769747B2

公开(公告)日：2023-09-26

申请号：US17350473

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Genki Sawada ,  Masayoshi Tagami ,  Jun Iijima ,  Ippei Kume ,  Kiyomitsu Yoshida

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L24/05 ,  H01L24/09 ,  H01L24/83 ,  H01L25/18 ,  H01L24/29 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05149 ,  H01L2224/05166 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/09515 ,  H01L2224/29186 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/83201 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.

公开(公告)号：US11532589B2

公开(公告)日：2022-12-20

申请号：US17010196

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Jun Iijima ,  Hiroshi Nakaki

IPC: H01L31/14 ,  H01L27/146 ,  H01L23/00 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.

公开(公告)号：US12068301B2

公开(公告)日：2024-08-20

申请号：US18297849

申请日：2023-04-10

Applicant: KIOXIA CORPORATION

Inventor： Jun Iijima ,  Yumi Nakajima

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

公开(公告)号：US11355512B2

公开(公告)日：2022-06-07

申请号：US16800163

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Masayuki Kitamura ,  Satoshi Wakatsuki

IPC: H01L23/532 ,  H01L21/768 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.

公开(公告)号：US11270980B2

公开(公告)日：2022-03-08

申请号：US16916979

申请日：2020-06-30

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US11729973B2

公开(公告)日：2023-08-15

申请号：US17160563

申请日：2021-01-28

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H10B43/27 ,  H01L25/065 ,  H01L23/00 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/04 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05095 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.