公开(公告)号：JP2011101334A

公开(公告)日：2011-05-19

申请号：JP2009293012

申请日：2009-12-24

Applicant: Denshi Buhin Kenkyuin ,  電子部品研究院Korea Electronics Technology Institute

Inventor： KIM YONG SEONG ,  SEO KYEUNG-HAK ,  CHO JIN WOONG ,  LEE HYUNSEOK ,  KWON TAIGIL ,  LIM YONGSEOK

IPC: H04B1/707

CPC classification number: H04J13/10

Abstract: PROBLEM TO BE SOLVED: To reduce an overall size by further decreasing a gate area not only by simplifying an entire configuration but also by accelerating an operating speed.
SOLUTION: A pseudo-orthogonal code generator includes: a serial/parallel converter for converting serial transmission data into parallel data for the unit of nine bits; a four-bit counter for repeatedly counting from 0 to 15; and a combination circuit unit for sequentially generating a pseudo-orthogonal code of 16 bits using the parallel data of nine bits and a four-bit counter value. Signal processing in the combination circuit unit is represented by a predetermined expression (0≤I≤15) of cb0(I), cb1(I), cb2(I), cb3(I), C(I) wherein C(I) is 0≤I≤15 as a pseudo-orthogonal code for the parallel data of nine bits, b0-b9 are the parallel data of nine bits, and i0-i3 are four-bit counter values binarized from the I which corresponds to an index for 16-bit pseudo-orthogonal code.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了通过进一步减小栅极面积来减小总体尺寸，不仅通过简化整体构造，而且通过加速操作速度。 解码：伪正交码发生器包括：串行/并行转换器，用于将串行传输数据转换成9位的并行数据; 一个从0到15重复计数的四位计数器; 以及组合电路单元，用于使用9位的并行数据和4位计数器值顺序地生成16位的伪正交码。 cb0（I），cb1（I），cb2（I），cb3（I），C（I）的预定表达式（0≤I≤15）表示组合电路单元中的信号处理，其中C（I） 作为9比特的并行数据的伪正交码，0≤I≤15，b0-b9是9比特的并行数据，i0-i3是从对应于索引的I二值化的四比特计数值 用于16位伪正交码。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：AU2003263620A1

公开(公告)日：2004-04-08

申请号：AU2003263620

申请日：2003-09-18

Applicant: KOREA ELECTRONICS TECHNOLOGY

Inventor： YOON CHAN-SOO ,  LIM SEUNG-OK ,  PARK YOUNG-CHOONG ,  CHOI KWANG-SOON ,  SEO KYEUNG-HAK ,  JUNG KWANGMO

IPC: H04L12/66 ,  H04L12/28 ,  H04L12/46 ,  H04L29/06 ,  H04M3/00 ,  H04M11/00

Abstract: The present invention relates to a communication system architecture which can perform integrated processing of different network protocols and multimedia traffics. The communication system for integrated processing of different network protocols and multimedia traffics comprises a common packet; a common packet switch; a plurality of channels; a common bus; a common protocol platform; an external network protocol converter; and an internal network protocol converter. Thus, the present invention can process traffics rapidly embodied by mean of hardware, and easily perform various QoS, traffic control, and so on by designing a unified common platform with an open architecture. In addition, the present invention can be used for digital consumer devices in building networks and home networks or various digital appliances classified as Internet information appliances, and for control systems such as a home gateway, a home server, an STB, a home station and so on.

公开(公告)号：AU2003282427A1

公开(公告)日：2004-06-18

申请号：AU2003282427

申请日：2003-11-25

Applicant: KOREA ELECTRONICS TECHNOLOGY

Inventor： CHOI KWANG-SOON ,  LIM SEUNG-OK ,  JUNG KWANGMO ,  SEO KYEUNG-HAK

IPC: H04L29/06

Abstract: The present invention provides common protocol architecture and methods for transmitting data between different network protocols and a common protocol packet. The common protocol architecture comprises an application layer; a common protocol layer positioned under the application layer, the common protocol layer enabling data communications between the different protocols; a presentation layer positioned under the common protocol layer; a session layer positioned under the presentation layer; a transport layer positioned under the session layer; a network layer positioned under the transport layer; a data link layer positioned under the network layer; and a physical layer positioned under the data link layer. The common protocol packet comprises a common protocol header with information about a packet and a payload with the contents of data. By designing the common protocol layer and the common protocol packet accepting various protocols simultaneously, the present invention can improve compatibility between different protocols.

公开(公告)号：EP1566036A4

公开(公告)日：2006-12-20

申请号：EP03774301

申请日：2003-11-25

Applicant: KOREA ELECTRONICS TECHNOLOGY

Inventor： CHOI KWANG-SOON ,  LIM SEUNG-OK ,  JUNG KWANGMO ,  SEO KYEUNG-HAK

IPC: H04L29/06 ,  H04L29/08

CPC classification number: H04L69/08

Abstract: The present invention provides common protocol architecture and methods for transmitting data between different network protocols and a common protocol packet. The common protocol architecture comprises an application layer; a common protocol layer positioned under the application layer, the common protocol layer enabling data communications between the different protocols; a presentation layer positioned under the common protocol layer; a session layer positioned under the presentation layer; a transport layer positioned under the session layer; a network layer positioned under the transport layer; a data link layer positioned under the network layer; and a physical layer positioned under the data link layer. The common protocol packet comprises a common protocol header with information about a packet and a payload with the contents of data. By designing the common protocol layer and the common protocol packet accepting various protocols simultaneously, the present invention can improve compatibility between different protocols.