公开(公告)号：JPH09163363A

公开(公告)日：1997-06-20

申请号：JP21123996

申请日：1996-08-09

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KAN HIDEYASU ,  KOU SHIYOUSHIYAKU ,  KEN YOSHIHIRO ,  RI TOUHO ,  CHIYOU SEIKOU

IPC: H04N5/06 ,  H03L7/00 ,  H03L7/06 ,  H03L7/085 ,  H04L7/033 ,  H04N5/04 ,  H04N5/12 ,  H04N5/44 ,  H04N7/62 ,  H04N19/00 ,  H04N19/42 ,  H04N19/70 ,  H04N19/80 ,  H04N19/85 ,  H04N21/43 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To provide a circuit with which a decoding clock(DC) is synchronized with an encoding clock(EC) in an MPEG system. SOLUTION: A VCO 11 changes the DC into the EC. A register part 12 stores and outputs a reference program clock signal(PCR) for multiplexing which is inputted for prescribed bits every time. A counter 13 is initialized by the PCR and generates a reference local program clock signal(LPRC). A substracter 14 for phase error control generates a signal for controlling the VCO 11 by performing the combining operation of PCR and LPCR.