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公开(公告)号：JPH09167970A
公开(公告)日：1997-06-24
申请号：JP21124096
申请日：1996-08-09
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KAN HIDEYASU , KEN YOSHIHIRO
Abstract: PROBLEM TO BE SOLVED: To convert each channel signal normalized to a specific level into an original size by receiving data A subjected to be inverse normalization, extracting inverse normalization information B to be multiplied with the data A from a storage means and multiplying the data A and the information B. SOLUTION: A control section 23 controls the entire section to store inverse normalization B to be multiplied with data A subjected to be inverse normalization and to store the data A to an input memory 24. A register 25 provides an output of the data A to the memory 24 properly synchronously with each other and a multiplexer 26 selects and outputs the information B corresponding to the data A among plural sets of information B stored in the ROM 21. A multiplier 22 multiplies the data A from the register 25 with the information B from the multiplexer 26 to store output data to an output a memory 29. Thus, each channel signal normalized to a specific level by multi-channel processing in converted into an original size by one multiplication to reduce the inverse normalization time.
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公开(公告)号：JPH09259115A
公开(公告)日：1997-10-03
申请号：JP29170596
申请日：1996-11-01
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KIN KENSHIYU , CHIYOU JIYUNKA , KEN YOSHIHIRO
Abstract: PROBLEM TO BE SOLVED: To convert respective inputted data into bit-serial data and speedily perform transposing operation for a matrix by storing respective registers with K/N-bit data selected by an output multiplexer module means, and then integrating N K/N-bit data into one data and outputting it as K-bit data. SOLUTION: A bit-serial transposing module means 12 selects and outputs shifted K/N-bit data, outputted by an input shift register module means 11, with a switching control signal. The output multiplexer module means 13 selects and outputs the K/N-bit data, outputted by the bit-serial transposing module means 12, by respective multiplexers. An output register module means 14 stores the respective registers with the K/N-bit data selected by the output multiplexer module means 13, and then integrates N K/N-bit data into one data, which is outputted as K-bit data.
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Patent Agency Ranking
公开(公告)号：JPH09212486A
公开(公告)日：1997-08-15
申请号：JP25333396
申请日：1996-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KAN HIDEYASU , KOU SHIYOUSHIYAKU , KEN YOSHIHIRO
Abstract: PROBLEM TO BE SOLVED: To provide a composition filter of a decoder which is improved in calculation speed and reduced in the use of an unnecessary memory. SOLUTION: The result of conversion of a 1st multiplier and accumulator 13 which performs the conversion by multiplying subband data in a 1st memory 16 and a cosine coefficient in a 1st ROM 15 by each other is stored in a 2nd memory 18 and copied to a 3rd memory 19, and the audio signal synthesized by processing the data stored in the 3rd memory and a window coefficient in a 2nd ROM 17 by a 2nd multiplier and accumulator 14 is stored in a first-in first-out part 20. Then this audio signal is restored by a digital-analog converter 21 to a sound signal, which is outputted to a speaker; and the multiplying and accumulating operations of the 1st and 2nd multiplier and accumulators 13 and 14 are controlled by a controller 10.
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公开(公告)号：JPH09167968A
公开(公告)日：1997-06-24
申请号：JP21124196
申请日：1996-08-09
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KAN HIDEYASU , SAI SHIYOUDA , KOU SHIYOUSHIYAKU , KEN YOSHIHIRO
IPC: H04N19/00 , H03M1/12 , H03M7/00 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/63 , H04N19/70 , H04S3/00
Abstract: PROBLEM TO BE SOLVED: To provide a composite decoding device simultaneously processing information sets sent from an MPEG-2 multi-channel audio decoder through dynamic cross coding and virtual coding. SOLUTION: The composite decoding device for the multi-channel audio decoder is provided with an arithmetic section 11 receiving a control word, information and a scale index from a first-in first-out means FIFO, calculating information depending on the presence of dynamic cross coding and virtual coding decided by the control word and providing an output to a duplicate photo memory and with a control section 12 generating a sequential control signal with respect to the operation to be conducted by the arithmetic section 11 based on the control word received from the first-in first-out means FIFO.
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公开(公告)号：JPH09167154A
公开(公告)日：1997-06-24
申请号：JP25333496
申请日：1996-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KAN HIDEYASU , KOU SHIYOUSHIYAKU , KEN YOSHIHIRO
Abstract: PROBLEM TO BE SOLVED: To input a lot of hybrid-decoded signals and to restore them to original signals through specified decoding conversion by performing dematrixing operation to the plural hybrid-decoded signals and filtering them through a low-pass filter(LPF). SOLUTION: In this dematrixing device for MPEG-2 multichannel audio decoder for 5.1 channel, an operation and control logic 20 sets five hybrid- decoded signals, namely, left side and right side signals L0 and R0 of stereo and three channel signals T2 -T4 for multichannel signal processing as inputs and performs the dematrixing operation for changing these signals into original signals, namely, left side and right side signals LW and RW of stereo, to which a weighted value is multiplied by an encoder, and respective center, left surround and right surround signals CW, LSW and RSW. Then, an IIR filter 30 sets an output signal xn from the operation and control logic 20 as an input and prepares a signal yn filtered through the LPF.
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公开(公告)号：JPH09163363A
公开(公告)日：1997-06-20
申请号：JP21123996
申请日：1996-08-09
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KAN HIDEYASU , KOU SHIYOUSHIYAKU , KEN YOSHIHIRO , RI TOUHO , CHIYOU SEIKOU
IPC: H04N5/06 , H03L7/00 , H03L7/06 , H03L7/085 , H04L7/033 , H04N5/04 , H04N5/12 , H04N5/44 , H04N7/62 , H04N19/00 , H04N19/42 , H04N19/70 , H04N19/80 , H04N19/85 , H04N21/43 , H04N7/24
Abstract: PROBLEM TO BE SOLVED: To provide a circuit with which a decoding clock(DC) is synchronized with an encoding clock(EC) in an MPEG system. SOLUTION: A VCO 11 changes the DC into the EC. A register part 12 stores and outputs a reference program clock signal(PCR) for multiplexing which is inputted for prescribed bits every time. A counter 13 is initialized by the PCR and generates a reference local program clock signal(LPRC). A substracter 14 for phase error control generates a signal for controlling the VCO 11 by performing the combining operation of PCR and LPCR.
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公开(公告)号：JPH07147613A
公开(公告)日：1995-06-06
申请号：JP14643694
申请日：1994-06-28
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KEN YOSHIHIRO , KIN ROUKOU , JIN HEIKIYOKU
Abstract: PURPOSE: To prevent the increase of the usable amount of the user of a prepaid card used for card type public telephone sets and, at the same time, to minimize the capacity of a memory which stores the usable amount. CONSTITUTION: A prepaid integrated circuit card is provided with a control section 20 which makes an input-output section 10 receive a new usable amount and instruction words for communication from a public telephone set 50 and discriminates whether or not an instruction word for communication received by means of the section 10 is the updating instruction of the usable amount stored in a memory 40. The control section 20 makes a comparator 30 compare the usable amount stored in the memory 40 with the new usable amount and controls the updating of the usable amount stored in the memory 40 based on the compared results.
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