Abstract:
A parallel receiving device and a method thereof using FPGA are provided to improve price competitive by suing the FPGA at low cost instead of an ASIC(Application Specific Integrated Circuit) for time and cost. A super-high parallel converter(110) generates a first deskew signal by sampling and dividing the input data signal into a first parallel signal. An FPGA(Field Programming Gate Array)(120) divides each first parallel signals into second parallel signals. The first deskew signal is divided into second deskew signals. The FPGA controls the skew between second parallel signals in consideration of second deskew signals. Second parallel signals in which skew is controlled are performed.
Abstract:
An apparatus for transmitting and receiving high-speed data having various data volumes are provided to interface a dependent signal selectively while stably receiving various high speed data. A dependent signal interface unit(130) converts dependent signals of various kinds into electrical signals of large volume through a medium and selectively interfaces the converted electrical signals through a high speed multi channel. A framer unit(120) receives the electrical signal to be selectively interfaced and multiplexes and maps the electrical signal by a giga bit unit to generate a multi channel frame signal. A transmission unit(110) receives the multi channel frame signal generated from the framer unit through the high speed multi channel to multiplex and transmit the multi channel frame signal by a serial signal of the set giga bit unit.