公开(公告)号：KR20080105399A

公开(公告)日：2008-12-04

申请号：KR20070052932

申请日：2007-05-30

Applicant: KOREA ELECTRONICS TELECOMM ,  KYUNGPOOK NAT UNIV IND ACAD

Inventor： LIM SANG KYU ,  KIM KANG WOOK ,  PARK HYUN ,  KO JE SOO

IPC: H03L7/16

CPC classification number: H03L7/101 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

Abstract: A method and an apparatus for synthesizing a frequency using a D-flip flop are provided to recover a synchronization state at high speed by feeding back an error and correcting the error when the synchronization is released. A frequency synthesizer includes a separating unit(120), an IF signal generator(130,131), and a D-flip flop frequency acquisition unit(140). A separating unit separates an output signal of an oscillator of a phase locked loop into two signals with phase difference of 90 degrees. The IF signal generator generates two IF signals by mixing the reference frequency of the phase-locked loop with two separated signals. The D-flip flop frequency acquisition unit applies two IF signals to the D- flip flop. The D-flip flop frequency acquisition unit controls the oscillator frequency based on the polarity of the phase difference of two applied signals.

Abstract translation: 提供了一种使用D触发器合成频率的方法和装置，以通过反馈错误并在同步被释放时校正错误来高速恢复同步状态。 频率合成器包括分离单元（120），IF信号发生器（130,131）和D触发器频率获取单元（140）。 分离单元将锁相环的振荡器的输出信号分离为相位差为90度的两个信号。 IF信号发生器通过将锁相环的参考频率与两个分离的信号混合来产生两个IF信号。 D触发器频率采集单元向D-触发器施加两个IF信号。 D触发器频率获取单元基于两个施加信号的相位差的极性来控制振荡器频率。

公开(公告)号：KR100903132B1

公开(公告)日：2009-06-16

申请号：KR20070128223

申请日：2007-12-11

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM JONG HO ,  SHIN JONG YOON ,  KO JE SOO

IPC: H04L12/28 ,  H04B1/06 ,  H04B10/12

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A parallel receiving device and a method thereof using FPGA are provided to improve price competitive by suing the FPGA at low cost instead of an ASIC(Application Specific Integrated Circuit) for time and cost. A super-high parallel converter(110) generates a first deskew signal by sampling and dividing the input data signal into a first parallel signal. An FPGA(Field Programming Gate Array)(120) divides each first parallel signals into second parallel signals. The first deskew signal is divided into second deskew signals. The FPGA controls the skew between second parallel signals in consideration of second deskew signals. Second parallel signals in which skew is controlled are performed.

Abstract translation: 提供了一种使用FPGA的并行接收装置及其方法，以便以低成本而不是ASIC（专用集成电路）为代价而花费时间和成本来提高价格竞争力。 超高并行转换器（110）通过将输入数据信号进行采样和分割为第一并行信号来产生第一偏移校正信号。 FPGA（场编程门阵列）（120）将每个第一并行信号划分为第二并行信号。 第一个偏斜消除信号分为第二个偏斜信号。 考虑到第二个偏移信号，FPGA控制第二个并行信号之间的偏差。 执行其中控制偏斜的第二并行信号。

公开(公告)号：KR20090017785A

公开(公告)日：2009-02-19

申请号：KR20070082198

申请日：2007-08-16

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SHIN JONG YOON ,  KO JE SOO ,  KIM JONG HO

IPC: H04L12/02 ,  H04L5/00

CPC classification number: H04J3/047

Abstract: An apparatus for transmitting and receiving high-speed data having various data volumes are provided to interface a dependent signal selectively while stably receiving various high speed data. A dependent signal interface unit(130) converts dependent signals of various kinds into electrical signals of large volume through a medium and selectively interfaces the converted electrical signals through a high speed multi channel. A framer unit(120) receives the electrical signal to be selectively interfaced and multiplexes and maps the electrical signal by a giga bit unit to generate a multi channel frame signal. A transmission unit(110) receives the multi channel frame signal generated from the framer unit through the high speed multi channel to multiplex and transmit the multi channel frame signal by a serial signal of the set giga bit unit.

Abstract translation: 提供一种用于发送和接收具有各种数据量的高速数据的装置，用于选择性地接合相关信号，同时稳定地接收各种高速数据。 依赖信号接口单元（130）通过介质将各种各样的相关信号转换成大体积的电信号，并且通过高速多通道选择性地接收经转换的电信号。 成帧器单元（120）接收要选择性地接口的电信号，并将电信号复用并映射到千兆比特单元，以产生多信道帧信号。 传输单元（110）通过高速多通道接收从成帧器单元产生的多信道帧信号，以通过设置千兆比特单元的串行信号复用并发送多信道帧信号。