公开(公告)号：JPH07297685A

公开(公告)日：1995-11-10

申请号：JP31732494

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU GIYONRIYUU ,  JIYO SEIIKU ,  SUNATORI MASUHIDE

IPC: H03K3/84 ,  G06F7/58 ,  H04B1/707 ,  H04J13/10 ,  H04L9/20

Abstract: PURPOSE: To simplify configuration requiring no additional circuit for inserting one additional bit into the output of a pseudo random number sequence (PN) by generating a new comparison value corresponding to a PN mask value, while using a comparison value translator. CONSTITUTION: After an initial LSSR load state signal has been received, a PN generator (LSSR) 100 executes shift operation, based on a sequential enable signal and generates a PN sequence. After the initial comparison value has been received, a comparison value translator 500 converts that value to a value corresponding to PN mask data. A comparator 200 compares the output of PN generator 100 with the converted comparison value. A D flip-flop 110, inverter 120 and an AND gate 130 are operated as a means for adding '0' of one bit at a prescribed bit position, after delaying the LSSR state value for one cycle when the LSSR state value is equal with the converted comparison value.