公开(公告)号：JPH08163116A

公开(公告)日：1996-06-21

申请号：JP31645094

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYO SEIIKU ,  KIN HOSHIMICHI ,  TEI KIHAN ,  SOU GENTETSU ,  RI KUNFUKU

IPC: H04M7/08 ,  H04J3/00 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE: To realize the frame synchronization device to demultiplex a time division multiplex signal in parallel from an STM-4C structure of a broad band overall information communication network in compliance with the ITU-T recommendations. CONSTITUTION: A serial parallel conversion circuit 10 and a byte arrangement circuit 30 detect a frame byte from high speed reception data at a transmission rate of 622 Mbps, align bytes based on a detected time and provides an output of frame data as 8-bit parallel data. A synchronizing signal pattern detection circuit 90 and a consecutive pattern confirmation circuit 100 detect frame bytes continuously based on a low speed clock obtained by applying 8 frequency division from an original clock signal at a frequency divider circuit 70 to seek a frame synchronizing signal. As a result, the power consumption is reduced and the amount of the hardware is decreased.

公开(公告)号：JPH07297685A

公开(公告)日：1995-11-10

申请号：JP31732494

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU GIYONRIYUU ,  JIYO SEIIKU ,  SUNATORI MASUHIDE

IPC: H03K3/84 ,  G06F7/58 ,  H04B1/707 ,  H04J13/10 ,  H04L9/20

Abstract: PURPOSE: To simplify configuration requiring no additional circuit for inserting one additional bit into the output of a pseudo random number sequence (PN) by generating a new comparison value corresponding to a PN mask value, while using a comparison value translator. CONSTITUTION: After an initial LSSR load state signal has been received, a PN generator (LSSR) 100 executes shift operation, based on a sequential enable signal and generates a PN sequence. After the initial comparison value has been received, a comparison value translator 500 converts that value to a value corresponding to PN mask data. A comparator 200 compares the output of PN generator 100 with the converted comparison value. A D flip-flop 110, inverter 120 and an AND gate 130 are operated as a means for adding '0' of one bit at a prescribed bit position, after delaying the LSSR state value for one cycle when the LSSR state value is equal with the converted comparison value.