公开(公告)号：JPH09181089A

公开(公告)日：1997-07-11

申请号：JP23296796

申请日：1996-09-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BIYUNRIYURU RIYUMU ,  TEHIYON HAN ,  DEOOKUHO CHIYOO ,  SUUMIN RII ,  KUWANYUI PIYUN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/70 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a super-self-aligned hetero junction bipolar transistor which can minimize an element size and improve element characteristics while simplifying its fabricating steps. SOLUTION: By excluding trenches for element isolation or separation and by a selective epitaxial growth process, a collector layer 7 and an emitter layer 17 are formed. Further, a spacer of an oxide film is provided between side walls of the collector and emitter layers 7 and 17 and side walls of films therearound to thereby clearly define an active region. Further, a metallic silicide base electrode film 14 is used to minimize a parasitic resistance of the base.