公开(公告)号：JPH09162200A

公开(公告)日：1997-06-20

申请号：JP21379996

申请日：1996-08-13

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： CHIYANSEOOKU RII ,  MINGUN KIMU ,  JIYONRAMU RII ,  KUWANYUI PIYUN ,  HIYONMUU PAAKU

IPC: H01L29/00 ,  H01L21/338 ,  H01L29/772 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To predict the high frequency noise characteristic of the change in the drain current by representing the change in the characteristic only with a fixed noise temp. independent of the drain current and the gradient of the equivalent noise conductance to the drain current. SOLUTION: The level of an input end noise voltage source is represented with the noise temp. of a gate intrinsic resistance and that of an output end noise current source represented with the drain equivalent noise conductance. The noise temp. of the gate intrinsic resistance is given by parameters represented with the gradient of the noise temp. to the drain current and the equivalent noise given by parameters represented with the equivalent noise conductance at drain current zero and gradient of the equivalent noise conductance to the drain current.

公开(公告)号：JPH09148269A

公开(公告)日：1997-06-06

申请号：JP17667296

申请日：1996-07-05

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIEONUTSUKU YAN ,  YUNGII OO ,  BIYUNSON PAAKU ,  CHIYURUSON PAAKU ,  KUWANYUI PIYUN

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L29/41 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a method of superimposing a T-shaped gate electrode and low-resistance metal whereby the productivity can be improved with a simple process. SOLUTION: A fine gate-photoresist film 12 is formed on specified part of a semiconductor substrate 11, insulation film 13 and flattening film 14 are formed thereon and etched to expose the film 13, this etched and exposed film 13 is etched and the exposed film 12 is etched. A gate metal 15 is vapor- deposited thereon, the film 14 is removed, and T-shaped gate metal 15 is vapor- deposited. Using this method, the insulation film and flattening film are formed on the semiconductor substrate and fine gate metal, the flattening film is etched back until the insulation film is exposed, the exposed region of the insulation film is etched to expose the reverse-sloped side face of the flattening film and low-resistance metal is vapor-deposited so as to have a directionality and lifted off.

公开(公告)号：JPH09181089A

公开(公告)日：1997-07-11

申请号：JP23296796

申请日：1996-09-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BIYUNRIYURU RIYUMU ,  TEHIYON HAN ,  DEOOKUHO CHIYOO ,  SUUMIN RII ,  KUWANYUI PIYUN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/70 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a super-self-aligned hetero junction bipolar transistor which can minimize an element size and improve element characteristics while simplifying its fabricating steps. SOLUTION: By excluding trenches for element isolation or separation and by a selective epitaxial growth process, a collector layer 7 and an emitter layer 17 are formed. Further, a spacer of an oxide film is provided between side walls of the collector and emitter layers 7 and 17 and side walls of films therearound to thereby clearly define an active region. Further, a metallic silicide base electrode film 14 is used to minimize a parasitic resistance of the base.