公开(公告)号：JPH0661339A

公开(公告)日：1994-03-04

申请号：JP11609392

申请日：1992-05-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SOUGEN ,  YANAGI KENKEI ,  KIYOU GENKIYUU

IPC: H01L21/304 ,  H01L21/02 ,  H01L21/74 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/535 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L21/76

Abstract: PURPOSE: To improve the area efficiency of a wafer by forming an SOI substrate where an arbitrary structure with electrical characteristics are buried between a seed wafer and a handle wafer. CONSTITUTION: Before a seed wafer 21 and a handle wafer 36 are joined, conductive or resistive films 27, 29, and 33 are evaporated in multiple layers on the seed wafer 21 and an arbitrary structure 32 (for example, a capacitor, a resistor, and a connecting wire) with electrical characteristics are formed individually or compoundly. Then, a surface where the structure 31 is formed is adhered to the handle wafer 36, thus manufacturing an SOI substrate and hence overlapping an arbitrary structure 31 inside an active region 37 but also wiring a metal wire on the upper and lower surfaces of the SOI substrate independently and hence improving the area efficiency of the wafer.

公开(公告)号：JPH0669450A

公开(公告)日：1994-03-11

申请号：JP33719992

申请日：1992-12-17

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SOUGEN ,  YANAGI KENKEI ,  KIYOU GENKIYUU ,  CHIYOU TOKUKOU

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: PURPOSE: To provide a method of the manufacture of a new construction dynamic memory device which has a high durability against the soft error and whose area efficiency is miximized. CONSTITUTION: After an active region is defined on a seed wafer (P-type substrate) and a 1st isolation oxide film is made to grow, a 2nd oxide film is formed. After substrate contact holes with which a buried structure and the active region are electrically connected to each other are formed and a capacitor polycrystalline Si layer is applied, an insulating film is made to grow and the patterns of channel-type capacitors 20a and 20b are formed. After a plate polycrystalline Si layer is buried in the substrate, the substrate is subjected to a mirror plane treatment and joined with a handle wafer having an insulating film. The substrate is ground to reduce the thickness, an anode polycrystalline Si contact hole region is formed, an anode linkage polycrystalline Si layer and an oxide film are successively formed and an anode linkage region is defined. A gate oxide film is made to grow, a polycrystalline Si layer is formed, word lines 33a and 33b are defined and side surface oxide films are formed. Ions are implanted in the upper part of the SOI 17 to form source regions 37a and 37b and a drain region 38. An oxide film 39 is formed and a drain contact hole 40 and an anode 42 are formed.