公开(公告)号：JPH07201734A

公开(公告)日：1995-08-04

申请号：JP28490994

申请日：1994-11-18

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI SHIYOUSHIYOU ,  IN ZENJIN ,  KIN HOYUU ,  KIYOU SOUGEN

IPC: B82Y10/00 ,  B82Y40/00 ,  H01L21/20 ,  H01L21/203

Abstract: PURPOSE: To provide a stainless, no-potential heterojunction thin film by remov ing an oxide film and a different kind of thin film from a V-groove part by using a selective dry etching method and then removing the remaining film of oxide. CONSTITUTION: On the surface of a single-crystal thin film 1, a pattern is formed which includes lines repeated at specific intervals. Then etching is carried out to form grooves (V-grooves), which are repeated at intervals corresponding to the line pattern and is sectioned into a V-shape on the surface of the single- crystal thin film 1. On this surface, a different kind of thin film 2 in a V-groove pattern, having a grating mismatched with the thin film 1 is grown. The majority or the whole of grating mismatching potential is locally distributed because of the presence of the V-grooves. On the different kind of thin film 2, an oxide film 3 is vapor-deposited. Then the oxide film 3 and the different kind of thin film 2 at the V-groove part where the potentials are locally distributed are removed, and furthermore the oxide film 3 is removed.

公开(公告)号：JPH0661339A

公开(公告)日：1994-03-04

申请号：JP11609392

申请日：1992-05-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SOUGEN ,  YANAGI KENKEI ,  KIYOU GENKIYUU

IPC: H01L21/304 ,  H01L21/02 ,  H01L21/74 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/535 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L21/76

Abstract: PURPOSE: To improve the area efficiency of a wafer by forming an SOI substrate where an arbitrary structure with electrical characteristics are buried between a seed wafer and a handle wafer. CONSTITUTION: Before a seed wafer 21 and a handle wafer 36 are joined, conductive or resistive films 27, 29, and 33 are evaporated in multiple layers on the seed wafer 21 and an arbitrary structure 32 (for example, a capacitor, a resistor, and a connecting wire) with electrical characteristics are formed individually or compoundly. Then, a surface where the structure 31 is formed is adhered to the handle wafer 36, thus manufacturing an SOI substrate and hence overlapping an arbitrary structure 31 inside an active region 37 but also wiring a metal wire on the upper and lower surfaces of the SOI substrate independently and hence improving the area efficiency of the wafer.

公开(公告)号：JPH07201806A

公开(公告)日：1995-08-04

申请号：JP29182194

申请日：1994-11-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： YASU KINEI ,  BOKU KEIKOU ,  MINAMI MOTOMORI ,  KIYOU SOUGEN

IPC: B41J2/135 ,  B44C1/22 ,  B44C3/00 ,  B81C1/00 ,  G02B1/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L29/84

Abstract: PURPOSE: To manufacture a structure which has a mechanical function into various constitution by combining together identical substrate or different kind substrate jointing technology and selective anisotropic etching technology and decreasing photographic transfer processes. CONSTITUTION: After a [110] substrate 110 and a [100] substrate 1102 are jointed together, the 100 substrate 1102 is formed into a thin film. On one surface of a substrate 1101, an etching protection mask 1103 is formed to form an etching window 1104. This is etched anisotropically in a KOH and EDP solution, and the etching is advanced while a [111] surface 1105 is exposed at right angles to the substrate surface. After the substrate 1101 is etched into a quadrilateral prism, the etching is continued on, while the bottom surface 1107 of the formed quadrilateral is regarded as an etching window. Then the etching advances only to the substrate 1102 positioned below the bottom surface 1107, and when a [111] sidewall 1108 is exposed, the etching is suppressed to form a truncated pyramidal structure 1109. A nozzle is thus manufactured.

公开(公告)号：JPH0758209A

公开(公告)日：1995-03-03

申请号：JP14673594

申请日：1994-06-28

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SOUGEN ,  HAKU TANEYASU

IPC: H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/41 ,  H01L29/86

Abstract: PURPOSE: To enhance recovery capacity of an antifuse element, even upon occurrence of a fusing error and to enhance the electrical conductivity of two electrodes after fusing. CONSTITUTION: This electrically programmable antifuse element for forming an electrode of two layer structure on a semiconductor substrate 1 formed with a functional element through an interlayer film comprises a field oxide 2 deposited on the semiconductor substrate 1, a first electrode 3 formed thereon in a specified pattern, a first insulator 4 deposited on the field oxide 2, while covering the first electrode 3 at the opposite ends thereof, a second insulator 5 deposited as an interlayer insulator on the exposed surface of the first electrode 3 between the first insulators 4, and a second electrode 6 formed on the second insulator 5.

公开(公告)号：JPH0669450A

公开(公告)日：1994-03-11

申请号：JP33719992

申请日：1992-12-17

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SOUGEN ,  YANAGI KENKEI ,  KIYOU GENKIYUU ,  CHIYOU TOKUKOU

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: PURPOSE: To provide a method of the manufacture of a new construction dynamic memory device which has a high durability against the soft error and whose area efficiency is miximized. CONSTITUTION: After an active region is defined on a seed wafer (P-type substrate) and a 1st isolation oxide film is made to grow, a 2nd oxide film is formed. After substrate contact holes with which a buried structure and the active region are electrically connected to each other are formed and a capacitor polycrystalline Si layer is applied, an insulating film is made to grow and the patterns of channel-type capacitors 20a and 20b are formed. After a plate polycrystalline Si layer is buried in the substrate, the substrate is subjected to a mirror plane treatment and joined with a handle wafer having an insulating film. The substrate is ground to reduce the thickness, an anode polycrystalline Si contact hole region is formed, an anode linkage polycrystalline Si layer and an oxide film are successively formed and an anode linkage region is defined. A gate oxide film is made to grow, a polycrystalline Si layer is formed, word lines 33a and 33b are defined and side surface oxide films are formed. Ions are implanted in the upper part of the SOI 17 to form source regions 37a and 37b and a drain region 38. An oxide film 39 is formed and a drain contact hole 40 and an anode 42 are formed.