公开(公告)号：DE4447142A1

公开(公告)日：1995-07-06

申请号：DE4447142

申请日：1994-12-29

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： CHANG DAE IG ,  KIM JEONG HO

IPC: H03L7/06 ,  H03D7/16 ,  H03L7/183 ,  H04B1/04 ,  H04B7/19 ,  H04B1/59 ,  H04B7/15

Abstract: A transmit reference oscillator, for a remote station of a VSAT for satellite communications, includes a divide-by-fifteen divider 22 for dividing input reference signals by 15; a Voltage Controlled Oscillator (VCO), a divide-by-four divider 26 for dividing the voltage controlled oscillator output, a divide-by-N divider 27 for dividing by N the output of divider 26; a phase detector 23; and a low pass filter 24 applying the filtered phase detector output to the voltage controlled oscillator. Accordingly, not only can data be transmitted over the whole of the band of 500 MHz which is the bandwidth for satellite communication transponders, without modifying remote station or a Radio Frequency (RF) part of a VSAT, but also the effect of phase noise and spurious interference can be minimised, and the oscillator can be simply implemented providing a reduced size and cost. A circuit 28 provides loop lock indication.

公开(公告)号：GB2285353A

公开(公告)日：1995-07-05

申请号：GB9425738

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： CHANG DAE IG ,  KIM JEONG HO

IPC: H03L7/06 ,  H03D7/16 ,  H03L7/183 ,  H04B1/04 ,  H04B7/19 ,  H03L7/18

Abstract: In the TRO(Transmit Reference Oscillator) for generating a reference frequency to transmit data about 500 MHz total bandwidth which is a bandwidth of a satellite communication relay, the apparatus comprises: a 15 dividing means 22 for dividing 5MHz reference signal locked from a hub station by 15, and outputting 333.3 KHz; a VCO(Voltage Controlled Oscillator) means 25 for inputting a filtered DC voltage, and outputting a transmit reference frequency; a 4 dividing means 26 for inputting the transmit reference frequency outputted from the VCO means 25, and dividing by 4; a CP(Control Processor) means 29 for outputting a divide rate control signal; a N dividing means 27 for outputting and dividing the 4 divided signal from the 4 dividing means 26 by N according to the divide rate control signal of the CP means 29; a phase detecting means 23 for comparing an output signal phase of the N dividing means 27 with an output signal phase of the 15 dividing means 22, and detecting its difference signal; a low pass filtering means 24 for filtering the phase difference signal detected from the phase detecting means 23, and outputting it into the VCO means 25; and an alarm generating means 28 for inputting the output signal of the 15 dividing means 22 and the output signal of the N dividing means 27, and generating an alarm signal according to a phase difference.