公开(公告)号：DE4018898A1

公开(公告)日：1991-01-10

申请号：DE4018898

申请日：1990-06-13

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： SHIN DONG KWAN

IPC: H03L7/06 ,  H03K7/06 ,  H03L7/081 ,  H03L7/089 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40

Abstract: This invention provides a digital auto-phase-controlled retiming circuit which automatically locates the retiming clock phase in the center of input data eye pattern by detesting the phase difference between retiming clock and data and tracking adoptively the mutual phase variation in a case that the mutual phase difference between data and retiming clock is uncertain and changes according to time in digital transmission and/or digital signal processing systems.

公开(公告)号：GB2233177B

公开(公告)日：1993-06-16

申请号：GB9010055

申请日：1990-05-04

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： SHIN DONG KWAN

IPC: H03L7/06 ,  H03K7/06 ,  H03L7/081 ,  H03L7/089 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40

Abstract: This invention provides a digital auto-phase-controlled retiming circuit which automatically locates the retiming clock phase in the center of input data eye pattern by detesting the phase difference between retiming clock and data and tracking adoptively the mutual phase variation in a case that the mutual phase difference between data and retiming clock is uncertain and changes according to time in digital transmission and/or digital signal processing systems.

公开(公告)号：GB2233177A

公开(公告)日：1991-01-02

申请号：GB9010055

申请日：1990-05-04

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： SHIN DONG KWAN

IPC: H03L7/06 ,  H03K7/06 ,  H03L7/081 ,  H03L7/089 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40

Abstract: A digital auto-phase-controlled retiming circuit automatically locates the retiming clock phase in the centre of an input data eye pattern by detecting the phase difference between the retiming clock and data, and tracking the mutual phase variation. Tracking occurs when the mutual phase difference between data and retiming clock is uncertain and changes with time e.g. in digital transmission and/or digital signal processing systems. The circuit comprises a phase detector / retimer U1, a loop processor U2 and a phase shifter U3. The phase detector1retimer U1 includes a gate (OR1, Fig 2) for receiving input data, a gate (OR2, Fig 2) for receiving an input retiming clock and a flip flop (FF2, Fig 2) for producing a retimed data signal.