Abstract:
Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.
Abstract:
Provided is a concentration ratio controlling apparatus for concentration type solar cells. The concentration ratio controlling apparatus may include a first condensing unit to primarily concentrate quantity of light that is irradiated from a light source; a second condensing unit disposed between a lower portion of the first condensing unit and a solar cell to secondarily concentrate the quantity of light that has passed through the first condensing unit and thereby irradiate the secondarily concentrated light toward the solar cell; an adjustment unit disposed in an optical path between the light source and the first condensing unit to adjust a concentration area of the first condensing unit based on an external force, and thereby adjust the quantity of light that is concentrated by the first condensing unit; and a control unit to analyze an input signal and thereby supply a corresponding drive control signal to the adjustment unit.
Abstract:
Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.
Abstract:
The present invention provides a chalcogenide phase-change material represented by the following Chemical Formula 1, and a memory device including the same. Ma(AxSbyTe(1-x-y))b [Chemical Formula 1] In Chemical Formula 1, M denotes an element having a doping formation energy ΔEf in a range of −3 eV/atom to 0.5 eV/atom, A denotes indium (In) or germanium (Ge), a and b are each positive numbers and selected to satisfy a+b=1, x ranges from 0.15 to 0.3, and y ranges from 0.05 to 0.25.
Abstract:
A method of manufacturing a phase-change random access memory includes: sequentially depositing an insulating layer, a first electrode layer, a phase change material layer, and a transfer material layer on a substrate; forming an array pattern in the transfer material layer using a laser interference lithography process; forming a metal layer on the transfer material layer having the array pattern formed; forming a second electrode layer by removing the transfer material layer; and forming a phase change layer by etching the phase change material layer using the second electrode layer as a mask. Accordingly, the manufacturing process of the phase-change random access memory may achieve an increase in speed and may be simplified.