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Patent Agency Ranking
公开(公告)号：JPH11284662A
公开(公告)日：1999-10-15
申请号：JP29515098
申请日：1998-10-16
Applicant: KOREA TELECOMMUN
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIN DAIKAN
Abstract: PROBLEM TO BE SOLVED: To provide the high-speed packet switch controller which is very suitable to a large-capacity packet switch controller and can maximize system performance through optimum switching by making use of the neural network chip. SOLUTION: A connection ring array 42 to which addresses generated by decoding a weighted value row address and a weighted value column address through a weighted value row address decoder 40 and a weighted value column address decoder 41 are inputted coupled an input signal to a neural network 43 according to the said address and also varies an output value according to an externally inputted weighted value. The neural network 43 outputs a crossbar switch control signal, generated by amplifying the signal outputted from the connection ring array 42, to the outside through an input/output bus 44.
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公开(公告)号：JPH10240850A
公开(公告)日：1998-09-11
申请号：JP26863997
申请日：1997-10-01
Applicant: KOREA TELECOMMUN
Inventor： HAN IL SONG
Abstract: PROBLEM TO BE SOLVED: To obtain a MOSFET analog integrating machine utilizing linearlized resistivity that actualizes high-speed operation and lowers the price of the manufacture by including a 2nd current mirror which is coupled with a 1st current mirror in parallel. SOLUTION: Through a 1st static current element and a 2nd static current element where currents almost as large as a current Im1 and a current Im2 flow, the final current IOUT is proportional to the product of voltages V1 and V2 . A bipolar transistor(BJT) is used for circuit constitution for finding the difference between the two currents Im1 and Im2 flowing to MOSFETs M1 and M2 operating in a triode area. Consequently, the circuit can be constituted through a BiCMOS process which is recently generalized. Namely, simple circuit design consisting of only a small number of transistors is obtained for ASIC- implementation as conventional problem points and high-speed analog operation can be actualized in some part in an element in all application fields.
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3.发明专利
公开(公告)号：JPH10240849A
公开(公告)日：1998-09-11
申请号：JP26750197
申请日：1997-09-30
Applicant: KOREA TELECOMMUN
Inventor： HAN IL SONG , SAI EIZAI , KIN DAIKAN
Abstract: PROBLEM TO BE SOLVED: To obtain the integrating machine with high performance which is able to operate at low voltage level, and the neural network synapse by using VLSI technology by including a 1st current mirror consisting of MOS transistors to generate a 1st current and a 2nd current mirror which consists of MOS transistors to generate a 2nd current and is coupled with the 1st current mirror in parallel. SOLUTION: An output current I0 fixes a supply voltage V1 and a voltage V3 applied to the gate of an n-channel MOSFET M2 of the 2nd current mirror. When a voltage V2 applied to the gate of an n-channel MOSFET M1 of the 1st current mirror is applied from outside, the final current I0 varies linearly with the current V2 . Namely, the output current I0 does not have a VT term as a secondary term, so this circuit is usable as an integrating machine. Further, elements are constituted in two stages between the supply voltage V1 and a ground voltage GND, so the loss of the voltage is small, so that low-voltage operation becomes possible.
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公开(公告)号：JPH10336034A
公开(公告)日：1998-12-18
申请号：JP26751097
申请日：1997-09-30
Applicant: KOREA TELECOMMUN
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIM DAE HWAN
Abstract: PROBLEM TO BE SOLVED: To execute fast analog arithmetic through the use of an analog voltage value by providing a pulse extracting means and an electric discharging means, etc., for discharging the current of an electric storing means while being fed back with the output of the pulse extracting means as a control means. SOLUTION: The pulse output of a pulse extracting part 13 is fed back as the control signal to turn on the third analog switch 140 of an electric charge discharging part 14. Thereby, the current of a capacitor 111 is discharged through an electric discharge adjusting part 141. This process continues until the voltage of the capacitor 111 becomes smaller than the reference voltage of a voltage comparator 121, and a pulse extraction part 13 outputs a pulse in the cycle of a master clock. Consequently, a voltage/pulse converter which is capable of fast analog arithmetic through the use of an analog voltage value in analog signal processing and analog/digital mix signal processing is obtained by changing a pulse by the voltage change of the capacitor 111.
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公开(公告)号：JPH10269309A
公开(公告)日：1998-10-09
申请号：JP27006797
申请日：1997-10-02
Applicant: KOREA TELECOMMUN
Inventor： HAN IL SONG
Abstract: PROBLEM TO BE SOLVED: To economically constitute a high density neural network neuron by analogically and directly constituting a circuit required for the continuous function conversion of a neural network output function and a ramp function and providing a differentiation possible function in an output function. SOLUTION: A controlled continuous ramp converter is constituted of three analog switches S1-S3 and two metal oxide film semiconductor electric field effect transistors M1 and M2. The on/off states of the analog switches S1-S3 are controlled by an input signal from an outside. When the analog switch S1 becomes the off-state and only the analog switch S2 becomes the on-state, a voltage V0 which is applied and stored in a capacitor C through the use of a transmission characteristic being equal to or below a critical value is utilized is limited to a max. value and a min. value by an operation controlled by the current I of the metal oxide film semiconductor electric field effect transistor M1 and the current I of the metal oxide film semiconductor electric field effect transistor M2 and respective approximate values of them are converted into the differentiation possible connecting function of an index function so as to be stored in the capacitor C.
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