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1.发明授权Path finding system for time-division multiplexed telephone communication network 失效用于时分多路复用电话通信网络的路径查找系统
公开(公告)号：US3718769A
公开(公告)日：1973-02-27
申请号：US3718769D
申请日：1970-06-29
Applicant: LANNIONNAISE D ELECTRONIQUE RO , CIT ALCATEL
Inventor： JACOB J
CPC classification number: H04Q11/08
Abstract: A path finding test device, more particularly for time switching, comprising input switches, intermediate switches and output switches, this device comprising a centralized memory representing the occupied or free state of all the intermediate switches so that the search for an available itinerary takes place by reading, in the memory, the free state of the intermediate switches. The invention may be applied to the telecommunication industry.
Abstract translation: 一种路径查找测试装置，更具体地涉及时间切换，包括输入开关，中间开关和输出开关，该装置包括表示所有中间开关的占用或空闲状态的集中式存储器，以便可用行程的搜索通过 在内存中读取中间开关的自由状态。
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2.发明授权
公开(公告)号：US3754100A
公开(公告)日：1973-08-21
申请号：US3754100D
申请日：1970-05-22
Applicant: CIT ALCATEL , LANNIONNAIS ELECTRONIQUE
Inventor： JACOB J
CPC classification number: H04Q11/08
Abstract: A time connection network comprises a structure consisting of several stages comprising at least an input stage, an intermediate stage and an output stage, connections existing between the input stage and the intermediate stage, and between the intermediate stage and the output stage, each stage being formed by a certain number of time switches each comprising a certain number of incoming lines and a certain number of outgoing lines, each incoming or outgoing line comprising several time channels and each time channel comprising several binary elements.
Abstract translation: 时间连接网络包括包括至少包括输入级，中间级和输出级的多个级的结构，存在于输入级与中间级之间的连接以及中间级与输出级之间的连接，每级是 由一定数量的时间开关形成，每个时间开关包括一定数量的输入线和一定数量的输出线，每个输入或输出线包括几个时间通道，每个时间通道包括几个二进制元素。
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公开(公告)号：US3794773A
公开(公告)日：1974-02-26
申请号：US26809072
申请日：1972-06-30
Applicant: LANNIONNAIS ELECTRONIQUE , CIT ALCATEL
Inventor： JACOB J , RENOULIN R , GUEZOU J
CPC classification number: H04J3/12 , H04J3/0629 , H04Q11/04
Abstract: A synchronizing unit for a time switching apparatus employs respective synchronizing elements for synchronizing communication time channels of multiplexed data signals. Both frame and multiframe sync recognition detection is effected on the basis of predetermined synchronizing time channels allotted within a frame. Speech channel and data signaling channel synchronization are also carried out on the basis of channel coding, so as to totally synchronize the data signals with the local clock of the time switching apparatus.
Abstract translation: 用于时间切换装置的同步单元使用用于同步多路复用数据信号的通信时间信道的各个同步元件。 基于在帧内分配的预定同步时间通道来实现帧和多帧同步识别检测。 语音信道和数据信令信道同步也是在信道编码的基础上进行的，以使数据信号与时间切换装置的本地时钟完全同步。
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公开(公告)号：US3727006A
公开(公告)日：1973-04-10
申请号：US3727006D
申请日：1971-02-10
Applicant: CIT ALCATEL
Inventor： JACOB J
Abstract: Test device comprising a central memory storing a record of the engaged states of the paths in a multi-stage switching network, consisting more particularly of a single memory block for two connection networks whose intermediate switches can receive data from the input switches of any of the networks, whereas they can transmit the said data only to the output switches of the network to which they belong.
Abstract translation: 测试设备包括存储多级交换网络中的路径的接合状态的记录的中央存储器，更特别地包括用于两个连接网络的单个存储器块，其中间交换机可以从任何一个的输入开关接收数据 网络，而它们只能将所述数据传输到它们所属的网络的输出交换机。
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公开(公告)号：GB1394894A
公开(公告)日：1975-05-21
申请号：GB3070272
申请日：1972-06-30
Applicant: LANNIONNAISE DELECTRONIQUE SOC , CIT ALCATEL
Inventor： JACOB J , RENOULIN R , GUEZOU J
Abstract: 1394894 Multiplex pulse code signalling SOC LANNIONNAISE D'ELECTRONIQUE and COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT ALCATEL 30 June 1972 [30 June 1971] 30702/72 Heading H4L A received multiplex signal has frame, speech channels and data signalling channels all synchronized by separate, independent but sequential processes. The multiframe Fig. 3A has 32 frames, each frame Fig. 2 has 32 time channels and each channel (I t 0 to I t 31 Figs. 6a, 6b, 6c, not shown) contains binary digits 1 to 8. The frames and multiframes are synchronized in a synchronizing unit 11, Fig. 1 (not shown) which generates (in 11) frame codes and multiframe codes to correspond with those contained in certain time channels of the received signal, and modifies these locally generated codes until they coincide in time with the received ones. Time channel I t 0 of every even frame contains the frame code; time channel I t 16 of the first frame TR0 of each multiframe Fig. 3a contains the multiframe code; time channel I t 16 of the remaining frames of each multiframe contains channel-by-channel signalling data (1-15, Figs. 3a, 3c) and further signalling data (16-31, Fig. 3a, 1-31, Fig. 3b). The Fig. 3a signal links a switching centre to a distant connection unit; Fig. 3b links two switching centres; Fig. 3c links a switching centre to a distant digital terminal. The synchronizing unit (11) and associated time connection network (18) are at the input to a time switching centre (20) which comprises a marker (20) which processes tests on new calls, using data supplied in the signalling channels; a local time base (23); and multirecorders (21A-21B) which process channel-by-channel data when connected to a concentrator. Inputs to the sync unit (11) are connection units (6, 7) for near and distant subscribers lines (12); junctors (8) for inter-exchange circuits (3); p.c.m. multiplex lines (10c for an electromechanical centre (4); and p.c.m. multiplex lines (10D) for a distant time centre 5. Frame and multiframe locking, Fig. 4.-The received time channels I t a 15, &c. Fig. 6A, are clocked into a register 101 by the distant clock W a and a decoder 103 provides the frame lock word at 104, and the multiframe lock word at 140. (a) Frame locking. Gates 106, 107 respectively indicate VTR, VTR if a frame lock word has been recognized, these gates being controlled by a "search" signal I to a W a8 a from a decoder 129 (at lower right). The VTR, VTR signals together with a further output of decoder 129, TRP (even frame), and with outputs PV i , ES i of the last of three cascaded bi-stables 123, 124, 125 control logic gates 112-122 which in turn govern setting and resetting of the same bi-stables 123-5. Of the various combinations of the states of the three bi-stables, three represent a state of search (PV i = 1); and three (ES i =1) represent synchronization of a counter 128 driven by the bi-stables and controlling the decoder 129. The bi-stables progress through the three states of search which represent the recognition of no, one, and two locking words until PV i and ES i change over and synchronization is established, the search signal I to /aW 8 /a ceasing. The other two states of synchronization represent loss of one and two locking words respectively. As soon as one word has been recognized during search, gate 127 blocks, and the ACT 1 changes. ACT 1 is used (top right) to ensure that loss of frame sync causes loss of multiframe sync. (b) Multiframe locking. Another counter and decoder 149, 151 responding to two cascade bi-stables 144, 145, have associated logic gates 142, 147 and inverters 141, 143. In response to the multiframe locking word at 140, and to outputs from the frame sync decoder 129, this circuit progresses through three conditions of sync, one loss of lock, and search. Speech channel synchronizing (Fig. 5a, not shown).-This is achieved by effectively reducing the last time channel I t 1 31 of the locally generated frame (Fig. 6a 4th line), and either reducing the ensuing first time channel I t 1 0 or lengthening it (Fig. 6B) according to whether the distant clock is fast or slow. The circuit basically consists of two stores (206, 207) respectively storing the first 15 time channels (1-15) and the last 15 (17-31), one being read while the other is receiving write-in, under the control of gates (208, 209, 230, 231). The circuit is controlled by a write address signal I ti from 128, Fig. 4 (received at 214), and a read address counter (241); together with various ones of locally generated clock signals W 1 -W 8 corresponding to the binary digits 1-8 of the locally generated time channels I t 10-31. A register (236) reads out the stores (206, 207) alternately under control of A, B outputs of a bi-stable (252). Channel-by-channel multiplex synchronizing (Fig. 7, not shown).-The I t 16 time channels of Figs. 3A, 3C which contain channel-by-channel signalling and are received from a distant digital terminal are synchronized (in Fig. 7) by a circuit (280, Fig. 12, not shown) which passes data only when the 8 bits of the 16th time channel are the same in two successive multiframes. The data is transmitted by 284 (Fig. 10, not shown) to a multirecorder (286). Channel-bychannel data received (at 287) from a time switching centre is received in (285. Fig. 11, not shown) and transmitted by 281 (Fig. 13, not shown) to a distant connection unit (278). Satellite "signalling data" synchronizing (Fig. 8, not shown).-The signalling data time channels of frames 16-31, Fig. 3A, and all frames Fig. 3B are received from a distant connection unit at 289 (Fig. 9B, not shown) in a register (61), and transferred to an active store (71). An order memory (78) selectively passes signalling data (from 71) to the control logic element (279, Fig. 8, not shown). A transmitter (289, Fig. 14, not shown) passes the received signalling data to a multiplex synchronizing module (not shown). Signalling data from the control logic unit (279) is transmitted to a distant connection unit (by 290+Fig. 9A) in which alternately a static memory (39) transmits orders, and an active memory (34) receives data, as controlled by an order signal (35).
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Patent Agency Ranking
公开(公告)号：SE344527B
公开(公告)日：1972-04-17
申请号：SE1064769
申请日：1969-07-29
Applicant: CIT ALCATEL , LANNIONNAIS ELECTRONIQUE
Inventor： JACOB J , LAVANANT P
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公开(公告)号：SE367743B
公开(公告)日：1974-06-04
申请号：SE923571
申请日：1971-07-16
Applicant: LANNIONNAIS ELECTRONIQUE , CIT ALCATEL
Inventor： LAVANANT P , JACOB J
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9.发明专利
公开(公告)号：CA932851A
公开(公告)日：1973-08-28
申请号：CA83379
申请日：1970-05-21
Applicant: CIT ALCATEL , LANNIONNAIS ELECTRONIQUE
Inventor： JACOB J
IPC: H04Q11/08
Abstract: A time connection network comprises a structure consisting of several stages comprising at least an input stage, an intermediate stage and an output stage, connections existing between the input stage and the intermediate stage, and between the intermediate stage and the output stage, each stage being formed by a certain number of time switches each comprising a certain number of incoming lines and a certain number of outgoing lines, each incoming or outgoing line comprising several time channels and each time channel comprising several binary elements.
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公开(公告)号：ZA8002656B
公开(公告)日：1981-05-27
申请号：ZA8002656
申请日：1980-05-02
Applicant: CIT ALCATEL
CPC classification number: H04L1/22 , H04Q11/0407
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