METHOD FOR MANUFACTURING MULTI-LEVEL CONDUCTIVE INTERCONNECTION FOR INTEGRATED CIRCUIT

    公开(公告)号:JP2001244336A

    公开(公告)日:2001-09-07

    申请号:JP2000368900

    申请日:2000-12-04

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a double etched multi-level interconnecting structure with a selective over layer. SOLUTION: The upper layer of a composite layer is prevented from being etched while it forms a multi-level interconnecting structure, with a selective over layer working as a mask. The method can solve the problems of a full-via first method and a partial-via first method, as the selective over layer forms a deep partial through-hole and an undeveloped photo resist prevents deposition during following manufacturing steps. Furthermore, the method has an advantage for flattening and polishing the double etched structure after depositing an electrically conductive layer that the selective over layer flattens effectively with controlling the depth of a trench.

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