公开(公告)号：JP2001244336A

公开(公告)日：2001-09-07

申请号：JP2000368900

申请日：2000-12-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  DRUMMOND ROBY MARY ,  VITKAVAGE DANIEL JOSEPH

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a double etched multi-level interconnecting structure with a selective over layer. SOLUTION: The upper layer of a composite layer is prevented from being etched while it forms a multi-level interconnecting structure, with a selective over layer working as a mask. The method can solve the problems of a full-via first method and a partial-via first method, as the selective over layer forms a deep partial through-hole and an undeveloped photo resist prevents deposition during following manufacturing steps. Furthermore, the method has an advantage for flattening and polishing the double etched structure after depositing an electrically conductive layer that the selective over layer flattens effectively with controlling the depth of a trench.

公开(公告)号：JPH11260785A

公开(公告)日：1999-09-24

申请号：JP33315198

申请日：1998-11-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MOLLOY SIMON JOHN ,  VITKAVAGE DANIEL JOSEPH

IPC: H01L21/302 ,  B08B7/00 ,  G03F7/42 ,  H01L21/304 ,  H01L21/311 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To eliminate a photoresist layer and its residue generated when viaholes are formed in an integrated device, by making etching residue water-soluble at a specified temperature by gas plasma treatment, and cleaning a substrate with deionized water. SOLUTION: A photoresist layer 31 is patterned in a selected region of a dielectric layer 30 by a photolithography process. The selected region of the dielectric layer 30 is controlled and etched by using an RIE plasma process and reactive etching agent, and obtained structure is arranged in a reaction vessel. A substrate and, in particular, the side wall of a viahole are exposed to mixed gas composed of oxygen, nitrogen and hydrofluorocarbon for about 60 seconds while energy of 1000 W is applied. The temperature is maintained at most 100 deg.C for the whole period, and residue is made soluble in water. Further, the pressure of the reaction vessel is reduced, the photoresist layer 31 is eliminated, the substrate is taken out and cleaning is performed by using deionized water.

公开(公告)号：GB2358734A

公开(公告)日：2001-08-01

申请号：GB0019969

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L27/00 ,  H01L21/316 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04

Abstract: A process for fabricating integrated circuit comprising dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100) is disclosed. The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2358733A

公开(公告)日：2001-08-01

申请号：GB0019968

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L21/768 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L27/00

Abstract: An integrated circuit comprises dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100). The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2350929A

公开(公告)日：2000-12-13

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure situated in window (101, Fig. 1) of dielectric layer (D 2 ) of an integrated circuit comprises lower electrode (102), dielectric layer (405) and upper electrode (406). The lower electrode (102) is disposed on side surface of cavity (101, Fig. 1), but not on the top surface of layer (D 2 ), and the top end of the lower electrode (102) is preferably about 0.2 microns below the top surface of the layer (D 2 ). The lower electrode (102) may be in contact with conductive plug (609), and the dielectric layer (405) is preferably tantalum oxide. A process for fabricating an integrated circuit is also disclosed, where lower capacitor plate (102) is deposited on both the sidewalls of the opening and the top surface of layer (D 2 ), and then the lower plate (102) is etched from the top surface and a portion of the sidewalls.

公开(公告)号：GB2350929B

公开(公告)日：2002-05-22

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.