METHOD FOR GENERATING ZERO RESET SIGNAL AND APPARATUS THEREFOR

    公开(公告)号:JP2000089179A

    公开(公告)日:2000-03-31

    申请号:JP20552399

    申请日:1999-07-21

    Abstract: PROBLEM TO BE SOLVED: To enable the automatic phase matching of input signals when there is a temperature change or aging of component elements by analyzing a modulation PTZ signal generated for the purpose of phase deviation of one of the input signals and phase matching of the input signals, thereby subjecting the input signals to phase matching. SOLUTION: A signal generator 11 generates an auxiliary signal which is supplied to the input C of a voltage control oscillator 2. Next, the RTZ signal RZ is modulated by a modulator 4. The periodic phase deviations lower average output power. The output signal (O) of the modulator 4 is supplied to a coupler 5. The coupler 5 couples and outputs the light signal having part of the energy of the output signal (O). The light signal which is coupled and outputted is supplied to an optical converter 6 and is converted to an electric signal. The electric signal is coupled to a low-pass filter 7. This low-pass filter 7 allows the passage of only the low-frequency signal. Consequently, the generated signal is mixed with the auxiliary signal of the signal generator 11 by a multiplier 8 and the demodulation of the generated signal is induced.

    2.
    发明专利
    未知

    公开(公告)号:DE60104974T2

    公开(公告)日:2005-09-01

    申请号:DE60104974

    申请日:2001-01-22

    Abstract: A method for correcting the phase of a clock in a data receiver, using a Hogge or Alexander phase discriminator which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) and a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single values (1,0) of different signal levels.

    3.
    发明专利
    未知

    公开(公告)号:DE60104974D1

    公开(公告)日:2004-09-23

    申请号:DE60104974

    申请日:2001-01-22

    Abstract: A method for correcting the phase of a clock in a data receiver, using a Hogge or Alexander phase discriminator which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) and a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single values (1,0) of different signal levels.

    6.
    发明专利
    未知

    公开(公告)号:DE60219277D1

    公开(公告)日:2007-05-16

    申请号:DE60219277

    申请日:2002-01-28

    Abstract: A decision feedback structure for recovering a bit stream out of received signals is contemplated, wherein the sampling instant may be tuned in dependence of the sequence or pattern of the preceding bits so as to follow the bit sequence dependent instant of the maximum eye opening. The decision-feedback equalizer structure comprises a signal input, decision means for making a bit value decision at a sampling instant, a feedback path to feed back bit values to said decision means and means for adapting the sampling instant for a bit value decision made by said decision means with respect to the sampling phase depending on the bit values of preceding bits, in particular depending on the bit value of the previous bit.

    8.
    发明专利
    未知

    公开(公告)号:DE60219277T2

    公开(公告)日:2008-01-03

    申请号:DE60219277

    申请日:2002-01-28

    Abstract: A decision feedback structure for recovering a bit stream out of received signals is contemplated, wherein the sampling instant may be tuned in dependence of the sequence or pattern of the preceding bits so as to follow the bit sequence dependent instant of the maximum eye opening. The decision-feedback equalizer structure comprises a signal input, decision means for making a bit value decision at a sampling instant, a feedback path to feed back bit values to said decision means and means for adapting the sampling instant for a bit value decision made by said decision means with respect to the sampling phase depending on the bit values of preceding bits, in particular depending on the bit value of the previous bit.

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