5.
    发明专利
    未知

    公开(公告)号:DE60104974D1

    公开(公告)日:2004-09-23

    申请号:DE60104974

    申请日:2001-01-22

    Abstract: A method for correcting the phase of a clock in a data receiver, using a Hogge or Alexander phase discriminator which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) and a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single values (1,0) of different signal levels.

    9.
    发明专利
    未知

    公开(公告)号:DE60104974T2

    公开(公告)日:2005-09-01

    申请号:DE60104974

    申请日:2001-01-22

    Abstract: A method for correcting the phase of a clock in a data receiver, using a Hogge or Alexander phase discriminator which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) and a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single values (1,0) of different signal levels.

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