公开(公告)号：GB2362029A

公开(公告)日：2001-11-07

申请号：GB0025340

申请日：2000-10-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KANE BRITTIN CHARLES ,  LAUGHERY MICHAEL A ,  MA YI

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

Abstract: A multi-layer spacer is formed adjacent a gate 301 of a FET structure. The multi-layer spacer includes a layer of low-k material 306 which reduces parasitic capacitance, and a layer of material which enables etch selectivity relative 307 to the substrate 101 and isolation oxides 301. The process helps avoid over-etching of active and isolation regions. The layers are preferably porous or carbon doped silicon dioxide 306 and silicon nitride 307. The transistor may be a lightly doped drain (LLD) structure.