公开(公告)号：JP2000208430A

公开(公告)日：2000-07-28

申请号：JP2000006222

申请日：2000-01-12

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SANDER SRINIVASAN CHETTLER ,  AISHIKKU C KIZURIYARI ,  MICHAEL A LARRY ,  MA YI ,  ALAN R MASSENGEERU ,  ROY PRADIP K

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To reduce hot carrier injection and deterioration by incorporating nitrogen of high concentration in an interface between a lightly doped drain structure and a gate oxide. SOLUTION: Lightly doped drain structures 36, 38 are formed by a first doping in source and drain regions 28, 30. After a spacer 40 is formed in a vertical sidewall 22 of a gate conductor region, source and drain injection matters 42, 44 which are deeper and wider than the lightly doped drain structures 36, 38 and whose dopant concentration is further high are formed in the source and drain regions 28, 30. The drain region 30 is annealed in atmosphere of at least one kind of nitrogen oxide, ammonia and dinitrogen monoxide. Thereby, nitrogen of high concentration can be incorporated in silicon/silicon dioxide interface between a gate oxide 24 and the lightly doped drain structure 38.

公开(公告)号：JPH11265887A

公开(公告)日：1999-09-28

申请号：JP33314998

申请日：1998-11-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  MERCHANT SAILESH M ,  ROY PRADIP K

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To enable a nitride layer to be released from its inner stress and set uniform in thickness by a method wherein a first sub-layer and a second sub-layer are deposited at different deposition rates, and this deposition process is repeatedly carried out a prescribed number of times to make the nitride layer as thick as required. SOLUTION: A nitride layer 16 is varied in deposition rate with time, a sequence of deposition starts at a low deposition rate and then transfers to a high deposition rate, and this deposition process is carried at deposition rates which are cyclically changed. A gate oxide structure comprises a first oxide layer 14, the nitride layer 16, and a second oxide layer 18. A deposition rate difference can be realized by changing, for instance, a pressure or a gas flow rate or both of them at the same time. For instance, a deposition process of low deposition rate is carried out at a temperature of 750 to 800 deg.C, and a deposition process of high deposition rate is carried out at a temperature of 800 to 850 deg.C. During a deposition term, these changes in deposition rate make deposited nitride serve as sub-layers. Interfaces between the sub-layers function as stress relaxation mechanisms in the gate oxide structure, whereby the multilayered nitride layer 16 is improved in uniformity, and pinholes and micro cracks present in the nitride films are lessened in number.

公开(公告)号：JP2001044140A

公开(公告)日：2001-02-16

申请号：JP2000189026

申请日：2000-06-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  MERCHANT SAILESH MANSINH ,  PRADIP KUMAR ROY

IPC: H01L21/283 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate dielectric structure which can increase the level of integration of an integrated circuit and can miniaturize the circuit by reducing the characteristic size of the circuit to avoid the problem which arises in an extremely thin silicon oxide film in the conventional structure, and a method for manufacturing the structure. SOLUTION: An integrated circuit has a gate stack structure, having a dielectric material layer 103 formed between a substrate 101 and a gate electrode 104. The layer 103 has a

公开(公告)号：JPH11261065A

公开(公告)日：1999-09-24

申请号：JP32557998

申请日：1998-11-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI

IPC: H01L21/283 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon gate FET where an interface between an oxide and a nitride is high in quality. SOLUTION: A gate forming dielectric layer composed of SiO2 13/Si3 N4 15 is formed on a silicon substrate 11. The composite oxide-nitride dielectric layer functions electrically as a uniformly grown oxide layer. The composite oxide-nitride dielectric layer is high in permittivity and capable of stopping boron from diffusion from a boron-loaded polysilicon gate through the intermediary of the gate dielectric layer. The manufacturing method is featured by that all the layers of the gate composite dielectric layer are processed in-situ, and that interfaces each between an SiO2 layer 13 and an Si3 N4 layer 14 and between the SiO2 layer 13 and the silicon substrate 11 can be kept high in quality, by making an LPCVD layer used for removing residual hydrogen undergo a post-annealing treatment.

公开(公告)号：JP2001094106A

公开(公告)日：2001-04-06

申请号：JP2000246577

申请日：2000-08-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALLEN YEN ,  MA YI

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To form a stable gate insulating layer for a high-speed silicon- germanium transistor. SOLUTION: In the epitaxial silicon-germanium layer of a two-layer substrate composed of a silicon substrate 40 and the silicon-germanium layer, a source region 48 and a drain region 50 which are separated from each other by a channel region 46 are demarcated adjacently to the channel region 46 by forming a masking layer for ion implantation on the channel region 46 and implanting dopant ions into the regions 48 and 50. After ion implantation, the channel region 46 is exposed, and a gate insulator layer composed of a silicon protective layer 58 and a gate oxide layer 60 is formed by masking the source and drain regions 48 and 50, the mask is removed and a gate 64 is formed.

公开(公告)号：JPH11195750A

公开(公告)日：1999-07-21

申请号：JP36648197

申请日：1997-12-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  ROY PRADIP K

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit device which is capable of using a high dielectric material having a high relative permittivity, by reducing defects and leakages thereof. SOLUTION: A method for manufacturing an integrated circuit having an oxidizable layer 2 with a surface has a step A of growing an oxide layer 3 on the surface of the oxidizable layer. The step A includes a step B of depositing a high k dielectric layer 4 on the grown oxide layer, and a step C of depositing an oxide layer 5 on the high k dielectric layer 4. The integrated circuit, which has the oxidizable layer 2 having the oxide layer 3 grown thereon, has the high k dielectric layer 4 on the grown oxide layer 3 and the oxide layer 5 deposited on the high k dielectric layer 4.

公开(公告)号：JP2001177090A

公开(公告)日：2001-06-29

申请号：JP2000328522

申请日：2000-10-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： BRITTAIN CHARLES KANE ,  MICHAEL A ROOFARII ,  MA YI

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer spacer close to the gate of FET structure. SOLUTION: Multilayer spacers 306 and 307 are provided with a low k material layer 306 for reducing floating capacitance, and a material layer 307 for indicating etching selectivity for a substrate and an insulation oxide. The method allows the overetching of active and insulation regions to be avoided.

公开(公告)号：JP2001024064A

公开(公告)日：2001-01-26

申请号：JP2000123012

申请日：2000-04-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  RADOSEVICH JOSEPH R ,  PRADIP KUMAR ROY

IPC: H01L21/3213 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To form a gate oxide layer with two types of thicknesses in a semiconductor device by allowing an oxygen diffusion barrier layer to check change of a second thickness of a gate oxide layer during formation of a first thickness of gate oxide. SOLUTION: A gate oxide layer 30 is formed to a predetermined first thickness 32 on a substrate 20, and an oxygen diffusion barrier layer 40 is deposited on the gate oxide layer 30. Thereafter, a photoresist mask is selectively patterned on the barrier layer 40. Then, a photoresist mask is removed, a gate- dielectric stack structure 10 is subjected to thermal oxidation process, and a new gate oxide layer 30 is formed on a first device 50. The gate oxide layer 30 is selectively formed to a second thickness 34 which is different from the first thickness 32. The oxygen diffusion barrier layer 40 deposited on the gate oxide layer 30 of a second device 60 checks further oxidation of the gate oxide layer 30.

公开(公告)号：JPH11289017A

公开(公告)日：1999-10-19

申请号：JP33315098

申请日：1998-11-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  MERCHANT SAILESH M ,  MINSEOKK O ,  ROY PRADIP K

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To obtain a CMOS gate structure in which a dopant does not creep at all treatment temperatures, by a method wherein a silicide which is annealed and treated is formed of large particle-size polysilicon of a lower multilayer structure. SOLUTION: After a polysilicon multilayer structure 20 is formed, a silicide layer 22 (WSix ) is deposited. The silicide layer 20 has a thickness of 50 Åor lower. After that, the silicide layer 22 is annealed and treated in an NH3 atmosphere, and the silicide layer 22 is nitrided. The silicide layer 22 functions as an intermediate dopant barrier layer in a final gate stack structure. After that, the second bulk deposition of the silicide layer 22 is performed, and a silicide layer 24 is deposited on the silicide layer 22 which has become the barrier layer. After that, a final annealing treatment is performed, the silicide layer 22 and the silicide layer 24 form a structure similar to the structure of the particle size of the polysilicon multilayer structure 20. Since the particle size is uniform, a dopant does not creep to the structure 20 irrespective of a treatment temperature.

公开(公告)号：JPH11121635A

公开(公告)日：1999-04-30

申请号：JP23675398

申请日：1998-08-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LEE JEAN LING ,  MA YI ,  MERCHANT SAILESH MANSINH

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To reduce a generation of counter-doping due to cross diffusion, by sequentially laminating a polysilicon blanket layer, a titanium layer, a titanium nitride layer and a fireproof metal silicide layer, and by forming a gate stack while patterning the laminate. SOLUTION: A first portion 171 of a polysilicon blanket layer 17 is a P-doped n gate, and a second portion 172 is a B-doped p gate. However, when the n gate comes in contact with the p gate, counter-doping occurs. To overcome this problem, the layer 17 is covered with a titanium layer 19. The layer 19 improves the gate resistance, so that a getter for B is provided. Note that a titanium nitride layer 21 forms a barrier against the diffusion of B and P, thereby preventing the occurrence of counter-doping. As a result of this gate structure, diffusion through a fireproof metal silicide layer 23 formed on the structure occurs little.