公开(公告)号：JP2001144289A

公开(公告)日：2001-05-25

申请号：JP2000304527

申请日：2000-10-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHIYOONNPIN CHIYAN ,  PAI CHIEN-SHING ,  VUONG THI-HONG-HA

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS device structure, whose gate length is smaller than 50 nm and a method of manufacturing the same. SOLUTION: This method comprises a first step, where a sacrificial gate is formed on the active region of a semiconductor substrate, a second step where the distance between a source region and a drain region inside the semiconductor substrate is prescribed by the width of the sacrificial gate, and a dielectric layer for a trench is formed adjacent to the sacrificial gate, a third step where the sacrificial gate is removed so as to form a trench in the dielectric layer as prescribed, a fourth step where a spacer is formed in the trench, and a fifth step where the gate of a device is so formed as to enable its part to be formed between the spacers.