公开(公告)号：JPH1197523A

公开(公告)日：1999-04-09

申请号：JP21635498

申请日：1998-07-31

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHIYOONNPIN CHIYAN ,  CHIENNSHIN PAI

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce sharp edges which may cause a current leakage in the device by a single oxidation step to round the edges of an Si at points where a trench oxide meets the lower face of a stress-releasing region directly formed on an Si substrate or other region. SOLUTION: An oxidation barrier region 34 is directly formed on a stress- releasing region 32 to avoid oxidizing a lower Si film during treating later, holes are formed in the film 34 and trenches 36 are formed by etching in an Si substrate 30 and an Si dioxide filler 38 is deposited in the trenches 36. After planarization step, it is oxidized to round the edges of Si at points where the trench Si dioxie 38 meets a pad oxide 32, the barrier region 34 and releasing region 32 are removed to form a gate oxide 42 on an active of the substrate 30, thereby reducing sharp edges which may cause a leakage current or bad edge effect.

公开(公告)号：JP2000223572A

公开(公告)日：2000-08-11

申请号：JP2000015643

申请日：2000-01-25

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHIYOONNPIN CHIYAN ,  CHEUNG KING PING ,  PAI CHIEN-SHING ,  ZHU WEI

IPC: H01L21/762 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/02 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce substantial capacitance connections present in a front-end structure up to first metal interconnect layer including a device substrate in a semiconductor device, such as a MOSFET, etc. SOLUTION: This device has a silicon substrate 12, an isolation structure 10 present in the substrate 12 (for example, a shallow trench isolation), an active element structure (for example, a transistor structure), a dielectric layer covering the active element structure, and a metal interconnect layer (a first metal layer) 28 covering the dielectric layer 26. At least, one of dielectric consisting layers in the front-end structure is provided with a material having a permittivity of less than 3.5. This material having relatively low permittivity reduces the capacitance connections in the front-end structure.

公开(公告)号：JP2001144289A

公开(公告)日：2001-05-25

申请号：JP2000304527

申请日：2000-10-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHIYOONNPIN CHIYAN ,  PAI CHIEN-SHING ,  VUONG THI-HONG-HA

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS device structure, whose gate length is smaller than 50 nm and a method of manufacturing the same. SOLUTION: This method comprises a first step, where a sacrificial gate is formed on the active region of a semiconductor substrate, a second step where the distance between a source region and a drain region inside the semiconductor substrate is prescribed by the width of the sacrificial gate, and a dielectric layer for a trench is formed adjacent to the sacrificial gate, a third step where the sacrificial gate is removed so as to form a trench in the dielectric layer as prescribed, a fourth step where a spacer is formed in the trench, and a fifth step where the gate of a device is so formed as to enable its part to be formed between the spacers.