公开(公告)号：EP1353373A3

公开(公告)日：2004-09-01

申请号：EP03100819.6

申请日：2003-03-28

Applicant: M/A-COM, INC.

Inventor： Goodrich, Joel Lee ,  Boles, Timothy Edward

IPC: H01L23/10 ,  H01L21/50

CPC classification number: B81B7/007 ,  B81B7/0006 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12034 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S438/928 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An electric component package (200) having a base (206) and a lid (208), the base and lid defining a hermetically sealed cavity (204) therebetween for accommodating an electric component (202) . The base (206) includes at least one conductive via (210) extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component (202) to be coupled to the conducive vias (210) to pass signals between the sealed cavity (204) and the exterior of the package without passing through the junction between the base (206) and lid (208). The electric component package (200) can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

公开(公告)号：EP1353373B1

公开(公告)日：2007-07-04

申请号：EP03100819.6

申请日：2003-03-28

Applicant: M/A-COM, INC.

Inventor： Goodrich, Joel Lee ,  Boles, Timothy Edward

IPC: H01L23/10 ,  H01L21/50

CPC classification number: B81B7/007 ,  B81B7/0006 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12034 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S438/928 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/45099

公开(公告)号：EP1605508A3

公开(公告)日：2007-12-12

申请号：EP05104934.4

申请日：2005-06-07

Applicant: M/A-COM, INC.

Inventor： Brogle, James Joseph ,  Boles, Timothy Edward ,  Goodrich, Joel Lee

IPC: H01L27/02 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0814 ,  H01L2224/16 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/00

Abstract: A chip-scale package (100) and method of manufacturing a chip-scale package are provided. The chip-scale package includes a mounting portion defined by a plurality of metal layers formed on each of a plurality of semiconductor regions (108) for mounting a device thereto. The mounting portions (104 and 106) are formed on a first side of the plurality of semiconductor regions. The chip-scale package (100) further includes a backside metal surface (110) formed on each of a second side of the plurality of semiconductor regions (108), with the plurality of semiconductor regions (108) providing electrical connection between the mounting portions (104 and 106) and the backside metal surfaces (110).

公开(公告)号：EP1605508A2

公开(公告)日：2005-12-14

申请号：EP05104934.4

申请日：2005-06-07

Applicant: M/A-COM, INC.

Inventor： Brogle, James Joseph ,  Boles, Timothy Edward ,  Goodrich, Joel Lee

IPC: H01L27/02 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0814 ,  H01L2224/16 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/00

Abstract: A chip-scale package (100) and method of manufacturing a chip-scale package are provided. The chip-scale package includes a mounting portion defined by a plurality of metal layers formed on each of a plurality of semiconductor regions (108) for mounting a device thereto. The mounting portions (104 and 106) are formed on a first side of the plurality of semiconductor regions. The chip-scale package (100) further includes a backside metal surface (110) formed on each of a second side of the plurality of semiconductor regions (108), with the plurality of semiconductor regions (108) providing electrical connection between the mounting portions (104 and 106) and the backside metal surfaces (110).

Abstract translation: 提供了芯片级封装（100）和芯片级封装的制造方法。 芯片级封装包括由多个金属层限定的安装部分，多个金属层形成在多个半导体区域（108）中的每一个上，用于将器件安装到其上。 安装部分（104和106）形成在多个半导体区域的第一侧上。 芯片级封装（100）还包括形成在多个半导体区域（108）的第二侧中的每一个上的背面金属表面（110），多个半导体区域（108）提供安装部分 （104和106）和背面金属表面（110）。

公开(公告)号：EP1353373A2

公开(公告)日：2003-10-15

申请号：EP03100819.6

申请日：2003-03-28

Applicant: M/A-COM, INC.

Inventor： Goodrich, Joel Lee ,  Boles, Timothy Edward

IPC: H01L23/10

CPC classification number: B81B7/007 ,  B81B7/0006 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12034 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S438/928 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An electric component package (200) having a base (206) and a lid (208), the base and lid defining a hermetically sealed cavity (204) therebetween for accommodating an electric component (202) . The base (206) includes at least one conductive via (210) extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component (202) to be coupled to the conducive vias (210) to pass signals between the sealed cavity (204) and the exterior of the package without passing through the junction between the base (206) and lid (208). The electric component package (200) can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

Abstract translation: 一种具有基座（206）和盖（208）的电气部件封装（200），所述基座和盖子在其间限定一个用于容纳电气部件（202）的气密密封腔（204）。 基座（206）包括延伸穿过其中的至少一个导电通路（210），允许与电气部件（202）相关联的控制和/或输入/输出（I / O）端口耦合到导通通孔（210）至 在密封空腔（204）和包装外部之间传递信号，而不通过基座（206）和盖（208）之间的接合点。 在将晶片分离成多个器件之前，可以使用传统的硅晶片集成电路制造机器在晶片级制造电子部件封装（200）。