公开(公告)号：JPH02202116A

公开(公告)日：1990-08-10

申请号：JP30635489

申请日：1989-11-24

Applicant: MARELLI AUTRONICA

Inventor： CHIESARIO CHIANCHI ,  JIYUZETSUPE CHIRIBERUTO

IPC: G01D5/244 ,  G01D5/245 ,  G01R19/175 ,  H03K5/1536

Abstract: PURPOSE: To improve reliability by providing a stopping means for immediately disabling a logic circuit after a first comparing means transmits a related signal indicating the zero cross of a sensor signal to the logic circuit. CONSTITUTION: This circuit is provided with a stopping means E for immediately disabling a logic circuit D after a first comparing means A transmits a related signal V1 to the logic circuit D. A time range in which the logic circuit D is opened by the operated result of the stopping circuit E ends at a point of time (t)0 , and therefore, it substantially precedes a point of time (t)1 when the operation pulling of the circuit E ends. Then, disturbance by any pulse with amplitude larger than a threshold level S1 fetched in the 'open' state of the logic circuit D can be avoided. Thus, when another zero cross signal is generated between the points of time (t)0 and (t)1 , an error can be identified, and reliability can be improved.