公开(公告)号：DE3852692T2

公开(公告)日：1995-08-03

申请号：DE3852692

申请日：1988-10-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUKUI YUKO ,  OHTANI KATSUHIRO ,  MIYAMOTO HIROYUKI ,  NISHIURA MASAO ,  CHIMURA MORIYUKI

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/52 ,  H01L27/04

Abstract: This invention is to realize a final circuit by wiring only the top layer depending on the individual circuits, by fabricating a master slice in the step of up to forming plural semiconductor elements such as transistors on a semiconductor substrate, forming a lower layer of versatile wiring pieces thereon, and forming contact holes thereon. In this way, since the step just before formation of the top layer wiring can be carried out regardless fo the features of individual circuits, preliminary mass productions are possible, and final products can be completed only by forming the wiring of the top layer depending on the requirements of the users. Accordingly, it is applicable to a wide variety of products, and the term for development and manufacture can be tremendously shortened.

公开(公告)号：DE3852692D1

公开(公告)日：1995-02-16

申请号：DE3852692

申请日：1988-10-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUKUI YUKO ,  OHTANI KATSUHIRO ,  MIYAMOTO HIROYUKI ,  NISHIURA MASAO ,  CHIMURA MORIYUKI

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/52 ,  H01L27/04

Abstract: This invention is to realize a final circuit by wiring only the top layer depending on the individual circuits, by fabricating a master slice in the step of up to forming plural semiconductor elements such as transistors on a semiconductor substrate, forming a lower layer of versatile wiring pieces thereon, and forming contact holes thereon. In this way, since the step just before formation of the top layer wiring can be carried out regardless fo the features of individual circuits, preliminary mass productions are possible, and final products can be completed only by forming the wiring of the top layer depending on the requirements of the users. Accordingly, it is applicable to a wide variety of products, and the term for development and manufacture can be tremendously shortened.

公开(公告)号：JPH0282647A

公开(公告)日：1990-03-23

申请号：JP23523388

申请日：1988-09-20

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： CHIMURA MORIYUKI

IPC: H01L21/60 ,  H01L21/301 ,  H01L21/82 ,  H01L27/118

Abstract: PURPOSE:To reduce the cost of a chip by forming an internal circuit section of a size corresponding to a circuit scale, input-output circuit sections, a wiring section shaped onto a fundamental circuit element not used, a bonding pad and a scribing lane onto a semiconductor substrate, over the whole surface of which fundamental circuit elements are spread. CONSTITUTION:Fundamental circuit elements are spread all over the whole surface on a semiconductor substrate, thus forming a master slice. An internal circuit section 13 as a circuit region shaped by fundamental circuit elements corresponding to a circuit scale, input-output circuit sections 14 having at least one function of an input or an output formed by the fundamental circuit elements and an external connecting circuit section 16 formed by bonding pads 15 for connecting external pins onto the fundamental circuit elements not used are shaped by electrode wirings. Scribing lanes 9 for cutting a chip are formed onto the fundamental circuit elements not used in the periphery of the external connecting circuit section 16. The region of the scribing lanes 9 is cut, thus acquiring a semiconductor integrated circuit. Accordingly, the waste of gates not used is prevented.

公开(公告)号：JPH01171248A

公开(公告)日：1989-07-06

申请号：JP33088587

申请日：1987-12-25

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SATOMI KATSUJI ,  CHIMURA MORIYUKI

IPC: H01L23/522 ,  H01L21/768

Abstract: PURPOSE:To reduce noises overlapping a substrate potential and to ensure stable operation of elements, by minimizing an element isolating region on the periphery of an interconnection channel region where it is contacted with I/O and internal cells while diffusing the same dopant as that of a silicon substrate in the residual region on the substrate, and forming an insulating oxide film thin enough to enable a contact hole to be provided. CONSTITUTION:A CMOS gate array has metallic interconnection 1 and an insulating oxide film 2 in a wide region. Particularly, the peripheral regions around I/O cell or internal gate elements are covered with the insulating oxide film 2 that is relatively thick. An interconnection channel region also has a structure A. The region of the structure A for isolating elements in the part where the interconnection channel region is contacted with the I/O and internal cells minimized, while most of the residual region is constructed into a structure B. The region of the structure B is covered with the insulating oxide film that is relatively thin, and an N dopant is diffused in the surface of the substrate for forming source and drain of an NMOS transistor. In this manner, a supply potential can be supplied to the N -type diffused section and the N-type substrate in the region of the structure B through a supply potential supplying metallic interconnection 1 and a contact hole.

公开(公告)号：JPH01109744A

公开(公告)日：1989-04-26

申请号：JP26706787

申请日：1987-10-22

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NISHIURA MASAO ,  OTANI KAZUHIRO ,  FUKUI YUUKO ,  CHIMURA MORIYUKI ,  MIYAMOTO HIROYUKI

IPC: H01L21/82 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

Abstract: PURPOSE:To reduce chip area, by arranging a plurality of a first layer wiring segments having, on end-portions, contact holes connecting a first and a second wirings, in the manner in which said contact holes on the first layer wiring segment are arranged in a line along the main wiring direction of the second layer wiring. CONSTITUTION:Contact holes 2 on a first layer wiring segment 1 connect a first layer wiring and a second layer wiring, without distinguishing whether a plurality of the first layer wirings are in a basic cell region or in a wiring region. These contact holes are regularly arranged in a line along the main wiring direction 4 of the second layer wiring. Therefore, the wiring interval rule of the second layer wiring can be set identical, for the basic cell region and the wiring region. As a result, the second layer wiring formed in the wiring region can be extended into the basic cell region in a line without being bent in the midway, so that special regions to adjust the wiring interval rule are unnecessitated. Thereby reducing chip area.

公开(公告)号：JPH01109742A

公开(公告)日：1989-04-26

申请号：JP26706587

申请日：1987-10-22

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUKUI YUUKO ,  OTANI KAZUHIRO ,  MIYAMOTO HIROYUKI ,  NISHIURA MASAO ,  CHIMURA MORIYUKI

IPC: H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: PURPOSE:To restrain the increase of chip area to a minimum, by setting the length of a first layer wiring having, on both ends, contact holes for connection with a second layer wiring, to a length necessary and sufficient to make two lines of the second layer wiring pass, and arranging said first layer wiring regularly on a master slice. CONSTITUTION:The first layer wiring 7, 11, 13 is provided, on both ends, with contact holes 9a, 9b, 15a-15d for connection with second layer wirings 6, 8, 10, 12, 14. The length of the first layer wiring is set to length necessary and sufficient to make pass two lines of second layer wiring 6, 8, 12, 14 which are kept, by an insulating film, electrically independent of the first layer wiring 7, 11, 13. Thus the first layer wiring segments of defined shape are constituted, which are regularly arranged on a master slice. Thereby shortening the time required for custom process after master slice process, and restraining the increase of chip area necessary for wiring.

公开(公告)号：JPS58200579A

公开(公告)日：1983-11-22

申请号：JP8453482

申请日：1982-05-18

Applicant: Matsushita Electronics Corp

Inventor： CHIMURA MORIYUKI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/78

CPC classification number: H01L29/78

Abstract: PURPOSE:To solve the problems such as the decrease of surge withstand voltages at the part of input-output due to alloy pits and the increase of input-output leaks due to surges by a method wherein an aluminum region and a source- drain region are electrically connected via a specific region. CONSTITUTION:A contact mask 3 with a substrate 7 is superposed at the part wherein the mask for the formation of the source-drain region 1 and a mask of poly Si 2 are superposed each other, and thus the impurity contained in the poly Si 2 is diffused into the substrate 7, resulting in the formation of an N region 4. In the region without the superposition with the poly Si 2, the impurity for source-drain is diffused, and the diffused region 1 for source-drain is formed. The poly Si 2, the diffused region 4, and the diffused region 1 for source-drain are connected via the superposition part 5 of diffused parts each other. Both are connected by forming aluminum 6 on the poly Si 2. It is impossible that the alloy penetrates the diffused part 4 and then reaches the substrate part 7 of the base, even when the alloy extends of the substrate by penetrating the poly Si 2.

Abstract translation: 目的：解决由于合金凹坑引起的输入输出部分的浪涌耐受电压降低以及由于激光引起的输入输出泄漏的增加的问题，其中铝区域和源极 - 漏极区域是 通过特定区域电连接。 构成：将具有基板7的接触掩模3叠加在用于形成源极 - 漏极区域1的掩模和多晶硅2的掩模彼此叠置的部分上，从而使多晶Si 2中所含的杂质 扩散到衬底7中，导致形成N + 4区域。在不与多晶硅2叠加的区域中，用于源极 - 漏极的杂质扩散，并且用于源极 - 漏极的扩散区域1 形成了。 多晶Si 2，扩散区域4和源极漏极扩散区域1经由扩散部分的叠合部分5相互连接。 两者都通过在多晶硅2上形成铝6而连接。即使当合金通过穿透多晶硅2延伸到基板上时，合金也不可能渗入扩散部分4然后到达基底的基板部分7。

公开(公告)号：JPS61208239A

公开(公告)日：1986-09-16

申请号：JP4899885

申请日：1985-03-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MAEDA HIDEO ,  CHIMURA MORIYUKI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/88

Abstract: PURPOSE:To avoid electrostatic breakdown and leakage current by a method wherein an element formed on a semiconductor substrate and Al of a bonding pad is connected by a polycrystalline silicon provided under the bonding pad. CONSTITUTION:An element separating oxide film 6 is formed on a substrate 1 and a silicon oxide film 3 is formed on it and a polycrystalline silicon 8 is made to grow. Again silicon oxide films 4 and 7 are formed and apertures are drilled at necessary positions and the connection is made by Al. With this constitution, even if an electrostatic breakdown voltage is applied to a terminal, the junction to the substrate 1 is hardly broken because of the existence of oxide film 6 between the silicon 8 and the substrate 1. Also, leakage to the substrate 1 is avoided.

公开(公告)号：JPS59124758A

公开(公告)日：1984-07-18

申请号：JP23412282

申请日：1982-12-29

Applicant: Matsushita Electronics Corp

Inventor： KENGAKU SETSUYA ,  CHIMURA MORIYUKI ,  FURUTA MASAO

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H03K19/177

CPC classification number: H03K19/17708

Abstract: PURPOSE:To make chip size smaller, and to enable operation at high speed, also by coupling a PLA circuit section and a gate array circuit section by a signal from a flip-flop circuit section reversible by a clock signal from one system of said circuit sections. CONSTITUTION:Dotted lines represented transfer paths for signals, asynchronous signals from the asynchronous drive system gate array circuit sections (B) are converted into synchronous signals by the flip-flop section (C), and the synchronous signals are transmitted over the PLA system circuit constitutional section (A). When signals from the PLA circuit section are coupled with the gate array circuit sections, the PLA circuit section is synchronized by the flip-flop circuit section and coupled with the gate array circuit sections because the PLA circuit section is driven synchronously. An asynchronous circuit can also be treated by adding informations from the gate array system circuits to a PLA system, and a circuit extending over a wide range can be constituted. A synchronous circuit is incorporated in a small region by incorporating it into the PLA.

Abstract translation: 目的：为了使芯片尺寸更小，并且能够高速运行，还可以通过来自触发电路部分的信号将PLA电路部分和门阵列电路部分耦合到可由来自所述电路的一个系统的时钟信号反相的信号 部分。 构成：虚线表示信号的传输路径，异步驱动系统门阵列电路部分（B）的异步信号由触发器部分（C）转换为同步信号，同步信号通过PLA系统电路 宪法条文（A）。 当来自PLA电路部分的信号与门阵列电路部分耦合时，PLA电路部分由触发器电路部分同步并与门阵列电路部分耦合，因为PLA电路部分被同步驱动。 也可以通过从门阵列系统电路向PLA系统添加信息来处理异步电路，并且可以构成在宽范围内延伸的电路。 同步电路通过将其并入PLA中而并入小区域中。

公开(公告)号：JPH01258460A

公开(公告)日：1989-10-16

申请号：JP8689488

申请日：1988-04-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： CHIMURA MORIYUKI

IPC: H01L21/822 ,  H01L27/04

Abstract: PURPOSE:To lower the current variation rate responsible for noises and thereby to protect transistors from noise-caused erroneous operations by a method wherein an adjusting circuit is provided to adjust transistors divided into groups so that they are staggered in their ON and OFF timing. CONSTITUTION:Output buffer transistors are divided into four groups. For the adjustment of the timing of gate signals from each of the transistors 23-26, 27-30 divided into four groups, changes are introduced into delay circuits A-D and into switching voltage levels. The ON and OFF timing is so designed that it may stagger from one to the other between the divided buffer transistors 23-30. This results in a decrease in the current variation rate, which eventually protects the buffer transistors 23-30 from operational errors due to power source noises.