公开(公告)号：US3573352A

公开(公告)日：1971-04-06

申请号：US3573352D

申请日：1968-04-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: H04N9/73 ,  H04N9/32

CPC classification number: H04N9/73

Abstract: This specification discloses a color television receiver wherein the white balance controlling reference color illumination occurring in a portion of the fluorescent screen is passed through three primary-color filters so as to be separated into ''''red,'''' ''''green'''' and ''''blue'''' light rays which are irradiated onto photosensitive elements so that variations in the filtered light rays are converted to electrical quantities to be fed back to the video circuit, thereby directly or indirectly controlling the color reproduction signal voltage to be applied to the color picture tube.

公开(公告)号：CA857522A

公开(公告)日：1970-12-01

申请号：CA857522D

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

公开(公告)号：DE1762098A1

公开(公告)日：1970-08-13

申请号：DE1762098

申请日：1968-04-05

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: H04N9/73 ,  H04N9/32

公开(公告)号：JPH01236642A

公开(公告)日：1989-09-21

申请号：JP6402488

申请日：1988-03-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: H01L21/027 ,  H01L21/30 ,  H01L21/66

Abstract: PURPOSE:To make it possible to forecast the stability of the supply of product, which is affected by the relative variability between elements, by a method wherein the same element patterns are not used all of the chips on a semiconductor slice and element patterns are contrived so as to be formed on at least some chips in such a way that their dimensions are shifted from each other. CONSTITUTION:A plurality of pieces of element patterns are formed on every chip 2 on a semiconductor slice 1 in such a way that the dimensions or the positions of the element patterns are given an artificially random value different from each other within a range specified arbitrarily from the dimension or the position of an element pattern which is used as a reference. For example, if a statiscal fluctuation specified from the central value in a design is given to resistances LA and LB and resistance widths WA wa and WB and resistors RA and RB are formed, the resistance values of the resistors RA and RB become dispersed statiscally from the central value. Thereby, an dispersion sample, which is found only in a long period of time in a standard process, can be easily obtained and the stability of the supply of product, which is affected by the relative variability between elements, can be forcast.

公开(公告)号：JPH03132039A

公开(公告)日：1991-06-05

申请号：JP27130589

申请日：1989-10-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HASEGAWA KOICHI ,  FUJITA YASUHIRO

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE:To manufacture a semiconductor device, which suppresses the reverse diffusion into the epitaxial layer of a buried impurity diffusion layer by introducing the impurities of the same conductivity as a semiconductor substrate into the buried impurity diffusion layer of opposite conductivity, dividing it into many minute areas. CONSTITUTION:An N -type buried impurity diffusion layer 6 is made in a P-type semiconductor substrate 5 by selective diffusion method. A P -type buried isolating impurity diffusion layer 7 is made such that it surrounds the N -type buried impurity layer 6, and at the same time with this, P -type impurities are introduced into the N -type buried impurity diffusion layer 6, being divided into the whole region of the N -type buried impurity diffusion layer 6 at the areal ratio, proportional to the ratio with N -type impurity concentration so as to form P -type buried impurity layers 7a. And, an N-type epitaxial layer 8 is made on the p-type semiconductor substrate 5, and it goes through the subsequent heat treatment process. Hereby, the concentration at the surface of the N -type buried impurity diffusion layer 6 can be reduced, thus the type buried impurity diffusion layer 6 of such structure that the reverse diffusion into N-type epitaxial layer 8 of the N -type buried impurity layer 6 is suppressed is made.

公开(公告)号：JPH01236619A

公开(公告)日：1989-09-21

申请号：JP6402688

申请日：1988-03-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/30

Abstract: PURPOSE:To make it possible to easily forecast the degree of feeding stability of a semiconductor device in the state of relative irregularity of an element by a method wherein an exposing operation, with which a semiconductor integrated circuit which detects the effect of the relative irregularity of an element, is conducted. CONSTITUTION:The element pattern measurements same as the design center value of one chip component and the pattern data of an element pattern position are memorized in a pattern data storing part 11. These pattern data is picked out each time one-chip exposing operation is conducted, and the variation which is statistically random by a random number is added to the pattern data in accordance with the irregularity characteristics to be given to the pattern every time a pattern data is received by a statistical irregularity giving functional part 12. This pattern data having said irregularity is fed to an exposure control part 13, an exposing operation is conducted on a photomask or a semiconductor slice using an exposure part 14 which the exposure is being controlled. Accordingly, the receiving of a bulky data is unnecessary, and the exposure of statistical pattern data can be conducted easily. As a result, the degree of stability of supply of manufactured articles can be forecast easily.

公开(公告)号：JPH01222444A

公开(公告)日：1989-09-05

申请号：JP4806788

申请日：1988-03-01

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: G03F1/00 ,  H01L21/027 ,  H01L21/30

Abstract: PURPOSE:To make it possible to forecast the stability of the supply of products by a method wherein the dimensions or positions of semiconductor element forming patterns are arranged over the whole unit semiconductor slice with an arbitrary variability by a statistical technique. CONSTITUTION:Patterns are included a plurality of pieces and the dimension or position of each pattern is arranged so as to have a random error value within a range specified arbitrarily from the dimension or position of a pattern which is used as a reference. When a trial product is made using such a mask, an irregular sample, which is found only in a very long period in a standard process, can be easily obtained, the stability of the supply of products, which is changed due to the relative variability of each element, not only can be forecast, but also an examination of the reliability of an applied apparatus using the semiconductor element is also facilitated and the reliability of the apparatus can be improved.

公开(公告)号：JPS5269582A

公开(公告)日：1977-06-09

申请号：JP14655475

申请日：1975-12-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO

IPC: H01L27/082 ,  H01L21/331 ,  H01L21/8228 ,  H01L27/04 ,  H01L29/08 ,  H01L29/72 ,  H01L29/73

Abstract: PURPOSE:Both longitudinal PNP transistor and laterial PNP transistor are constituted within single semiconductor substrate, and these transistors are cascodeconnected in series. As a result, a circuit which can be considered as single PNP transistor featuring high voltage resistance as well as large current amplification ration can be obtained.

公开(公告)号：JPS52119802A

公开(公告)日：1977-10-07

申请号：JP3689376

申请日：1976-04-01

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJITA YASUHIRO ,  TAKAHAGI KAZUO

IPC: H01L21/822 ,  H01L27/04 ,  H04M9/00

Abstract: PURPOSE:To prevent the mutual interference between a low-frequency oscillator circuit part and a differential input type low-frequency amplified output circuit part in a semiconductor IC circuit in which the low-frequency oscillator part and the differential input type amplified output part are integrated in a single semiconductor substrate.