公开(公告)号：US6271070B2

公开(公告)日：2001-08-07

申请号：US20656198

申请日：1998-12-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOTANI NAOKI ,  SHIMIZU KEIICHIRO

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L21/8238

CPC classification number: H01L21/763 ,  H01L21/76202 ,  H01L21/8249

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract translation: 在具有双极晶体管形成区域和MOS晶体管形成区域的p型硅衬底的主表面上，生长外延层并形成n型掩埋层。 在形成穿透掩埋层的沟槽之后，在沟槽中形成掩埋多晶硅层。 然后，形成每个MOSFET的阈值控制层，穿通停止层，沟道阻挡层，n型阱层和p型阱层。 此时，由于通过高能离子注入形成了阱层，因此能够抑制n型掩埋层的扩大，能够缩短形成沟槽所需的时间。 因此，提供了制造半导体器件的实用方法。

公开(公告)号：JPH11243153A

公开(公告)日：1999-09-07

申请号：JP34138798

申请日：1998-12-01

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOTANI NAOKI ,  SHIMIZU KEIICHIRO

IPC: H01L21/76 ,  H01L21/8222 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To restrain formation time to within a practicable range of time in a method of manufacturing a Bi-CMOS device having a trench isolation structure. SOLUTION: An epitaxial layer 7 is grown on the primary surface of a P-type silicon substrate 1, having a bipolar transistor forming region Rbp and a MOS transistor forming region Rmos, and N-type embedded layers 81 and 82 are formed. Furthermore, a trench is formed penetrating through the edges of the buried layers 81 and 82, an embedded polysilicon layer 18 is formed being filled into the trench, and the threshold control layers 23 and 28 of MOSFETs, a punch-through stopper layer 24, channel stopper layers 25 and 29, an N-type well layer 26, and a P-type well layer 30 are formed. At this point, the well layers 26 and 30 are formed by the implantation of high energy impurity ions, so that the N-type embedded layers 81 and 82 are restrained from expanding in size, a trench can be formed in a shorter time, and a practicable manufacturing method can be realized.

公开(公告)号：JPH04114464A

公开(公告)日：1992-04-15

申请号：JP23493090

申请日：1990-09-04

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L29/43

Abstract: PURPOSE:To reduce the effect, of distribution of a current which flows through a resistive film by a method wherein a resistive film formed on an insulating film deposited on a semiconductor substrate and a first and a second electrode connected to both the end side faces of the resistive film are provided. CONSTITUTION:As the end side faces 6 and 7 of a resistive film 2 are brought into contact with electrodes 8 and 9, a current flows through the resistive film 2 uniformly in a thicknesswise and a widthwise direction, in result the film 2 becomes constant in resistance independent of current density. A resistive film 2 is protected against error in resistance caused by the error of a contact opening in dimension when the contact opening is provided onto the primary surface of the resistive film. Therefore, the resistance R of the resistive film 2 can be represented by a formula, R=2.RC+RS (L/W), where RC denotes the sheet resistance of the film 2, and RS is contact resistance between the end side faces 6 and 7 of the resistive film 2 and the electrodes 7 and 8.

公开(公告)号：JPH0374867A

公开(公告)日：1991-03-29

申请号：JP21095689

申请日：1989-08-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/94

Abstract: PURPOSE:To enable capacity to be adjusted to a desired value accurately by connecting a PN junction capacity to one side of two insulation film capacitors which are connected in parallel in series and controlling it with voltage which is applied to both edges for allowing the entire synthesized capacity to be varied. CONSTITUTION:A semiconductor film such as a polycrystal silicon film is allowed to grow on a field insulation film 1 such as a silicon oxide film, and an N-type impurities is injected for selecting etching, thus forming an N type semiconductor film 2. Then, a capacitor insulation film 3 such as silicon oxide film is formed by the CVD method, etc. Then, an N type semiconductor film 4 and a P type semiconductor film 5 are formed by the similar means as in the film 2. Further, silicon oxide film, etc., is accumulated as an interlayer insulation film 6, a contact window opening is performed, and a metal such as aluminum is deposited for selective etching, thus forming a signal electrode 7, a common electrode 8, and a control electrode 9. Controlling voltage applied between the electrodes 8 and 9 allows capacity between the electrodes 7 and 8 to be adjusted highly accurately.

公开(公告)号：JPH01280311A

公开(公告)日：1989-11-10

申请号：JP11111488

申请日：1988-05-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L21/22 ,  H01L21/324

Abstract: PURPOSE:To acquire a heating furnace which can heat all the semiconductor wafers uniformly in a short time by providing a high frequency induction furnace which makes the whole semiconductor uniform at a front stage of a semiconductor wafer input port 9 and by providing an electric heating furnace which carriers out heat treatment at a rear stage. CONSTITUTION:A high frequency induction furnace 1 is provided which heats a whole semiconductor wafer 8 uniformly at a short time at a front stage of a semiconductor wafer input port 9, and an electric furnace 2 for heat treatment is provided at a rear stage. For instance, one quartz tube 3 is located in a middle of the high frequency induction furnace 1 and the electric furnace 2. A high frequency coil 4 is wound around the quartz tube 3 in a region of the high frequency induction furnace 1 and the both ends thereof are connected to a high frequency power source 5. Moreover, a heater 6 is wound around the quartz tube 3 in a region of the electric furnace 2 and the both ends thereof are connected to a commercial frequency power source 7 of 50Hz or 60Hz. A gas introduction tube 10 is provided to the opposite side of the semiconductor input port 9 and the quartz tune 3 is covered with an insulating material 11.

公开(公告)号：JP2558472B2

公开(公告)日：1996-11-27

申请号：JP20412187

申请日：1987-08-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/72 ,  H01L29/732

公开(公告)号：JP2557522B2

公开(公告)日：1996-11-27

申请号：JP7109589

申请日：1989-03-22

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H02H9/04 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003

公开(公告)号：JPH0582728A

公开(公告)日：1993-04-02

申请号：JP24305991

申请日：1991-09-24

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L27/04 ,  H01L21/822

Abstract: PURPOSE:To provide a reliable capacitor that is less liable to discontinuity in its upper conducting film at the contact to the lower conductor. CONSTITUTION:A capacitor includes a lower conducting layer of an n polycrystalline film 13 formed on an insulating film 14, and a capacitor dielectric of a silicon nitride film 16 self-aligned in a window 15 opened in the insulating film 14. The silicon nitride film 16 is not deposited in the periphery of a contact hole 17 to prevent breaks in aluminum wiring near the contact hole. Therefore, the capacitor has reliable quality.

公开(公告)号：JPH0319236A

公开(公告)日：1991-01-28

申请号：JP15345289

申请日：1989-06-15

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE:To improve mutual conductance by arranging a second conductivity type base region and a first conductivity type drain region in a first conductivity type collector region, and electrically connecting a source region, a substrate region, and an emitter region. CONSTITUTION:A P-type well 2 is formed on an epitaxial layer 1; after a gate insulating film 3 is formed, polysilicon is deposited on the surface of a wafer, and impurity is added to the silicon film, thereby turning it into a sheet resistor; by selectively etching the polysilicon film, a gate electrode 4 is formed, and by ion implantation, a P type base diffusion layer 5 is formed; by ion implantation, an N type collector contact diffusion layer 6, an N type emitter diffusion layer 7, an N type source diffusion layer 8, and an N type drain diffusion layer 9 are formed; an interlayer insulating film 10 is formed; a contact window is made; by using aluminum, a base gate.common electrode 11, an emitter electrode 12, a collector electrode 13, and a source substrate electrode 14 are formed. Thereby current characteristics can be improved.

公开(公告)号：JPH02250629A

公开(公告)日：1990-10-08

申请号：JP7109589

申请日：1989-03-22

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SHIMIZU KEIICHIRO

IPC: H02H9/04 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003

Abstract: PURPOSE:To protect a semiconductor circuit against a surge up to a using time after mounting and to separate a protective circuit from an inner circuit by melting a fuse after starting to use it by providing a fuse between the protective circuit and the inner circuit. CONSTITUTION:A protective circuit pad 11 is connected to protection diodes 13, 14 and a fuse 15 through a protective resistor 12. The other end of the fuse 15 is connected to an inner circuit connecting pad 16, and connected to an inner circuit 18 through a resistor 17. While the fuse 15 is not melted, a protective circuit 19 formed of the resistors 12, 17 and the diodes 13, 14 protect the circuit 81. When the pad 16 is grounded, a positive voltage is applied to the pad 11 and the fuse 15 is melted, the circuit 19 is separated from the circuit 18, thereby removing influence of the circuit 19.