公开(公告)号：DE69610368T2

公开(公告)日：2001-01-25

申请号：DE69610368

申请日：1996-06-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NOMA ATSUSHI ,  UEDA DAISUKE

IPC: H01G4/12 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/92

Abstract: A ferroelectric capacitor comprising a lower electrode (13A), a ceramic capacity film (14A) made of a ferroelectric substance and an upper electrode (15A) is provided on a substrate insulating film (12) formed on a semiconductor substrate (11). A layer insulating film (16) is formed on the semiconductor substrate so as to cover the ferroelectric capacitor. An electrode wiring (17) is formed on the layer insulating film (16). A length L of the surface of the ceramic capacity film which is present between an intersection of the side of the upper electrode (15A) and the upper face of the ceramic capacity film (14A) and an intersection of the side of the ceramic capacity film (14A) and the upper face of the lower electrode (13A) and a thickness D of the ceramic capacity film (14A) have a relationship of L >/= 2D.

公开(公告)号：DE69610368D1

公开(公告)日：2000-10-26

申请号：DE69610368

申请日：1996-06-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NOMA ATSUSHI ,  UEDA DAISUKE

IPC: H01G4/12 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/92

Abstract: A ferroelectric capacitor comprising a lower electrode (13A), a ceramic capacity film (14A) made of a ferroelectric substance and an upper electrode (15A) is provided on a substrate insulating film (12) formed on a semiconductor substrate (11). A layer insulating film (16) is formed on the semiconductor substrate so as to cover the ferroelectric capacitor. An electrode wiring (17) is formed on the layer insulating film (16). A length L of the surface of the ceramic capacity film which is present between an intersection of the side of the upper electrode (15A) and the upper face of the ceramic capacity film (14A) and an intersection of the side of the ceramic capacity film (14A) and the upper face of the lower electrode (13A) and a thickness D of the ceramic capacity film (14A) have a relationship of L >/= 2D.

公开(公告)号：DE69316314T2

公开(公告)日：1998-06-04

申请号：DE69316314

申请日：1993-10-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OISHI YOSHIRO ,  UEDA DAISUKE

IPC: H01L21/338 ,  H01L23/482 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/812 ,  H01L29/41

Abstract: A semiconductor device operating at a high frequency, includes: a semiconductor layer; a first electrode for being applied with a voltage to control a current flowing in the semiconductor layer; a second electrode and a third electrode electrically connected to the semiconductor layer, at least one of the second and third electrodes being elongated above the first electrode to form a hollow around the first electrode by surrounding the first electrode with the second and third electrodes and the semiconductor layer; a passivation film formed over the second and third electrodes; and wherein the first electrode is directly in contact with an atmosphere in the hollow.

公开(公告)号：DE69316314D1

公开(公告)日：1998-02-19

申请号：DE69316314

申请日：1993-10-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OISHI YOSHIRO ,  UEDA DAISUKE

IPC: H01L21/338 ,  H01L23/482 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/812 ,  H01L29/41

Abstract: A semiconductor device operating at a high frequency, includes: a semiconductor layer; a first electrode for being applied with a voltage to control a current flowing in the semiconductor layer; a second electrode and a third electrode electrically connected to the semiconductor layer, at least one of the second and third electrodes being elongated above the first electrode to form a hollow around the first electrode by surrounding the first electrode with the second and third electrodes and the semiconductor layer; a passivation film formed over the second and third electrodes; and wherein the first electrode is directly in contact with an atmosphere in the hollow.

公开(公告)号：DE3324017A1

公开(公告)日：1984-01-05

申请号：DE3324017

申请日：1983-07-04

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA DAISUKE ,  TAKAGI HIROMITSU

IPC: H01L21/336 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/18

Abstract: An insulating-layer field-effect transistor, for example a power MOSFET, is manufactured by forming a rectangular prism-type recess in one direction so that the side walls of the recess form an angle of 45 DEG to the direction of the silicon substrate with the (100) plane as principal surface and the vertical side walls of the (010) or (001) plane is used as channel zone of the insulating-layer field-effect transistor, thereby ensuring a high electron mobility in the channel and, consequently, a low channel resistance, these being advantageous for high-power operation.

公开(公告)号：CA2249062C

公开(公告)日：2005-01-11

申请号：CA2249062

申请日：1998-09-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： TANAKA TSUYOSHI ,  NOMA ATSUSHI ,  ISHIDA HIDETOSHI ,  FURUKAWA HIDETOSHI ,  UEDA DAISUKE

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/338 ,  H01L21/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/812

Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

公开(公告)号：CA2249062A1

公开(公告)日：1999-04-01

申请号：CA2249062

申请日：1998-09-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA DAISUKE ,  ISHIDA HIDETOSHI ,  FURUKAWA HIDETOSHI ,  NOMA ATSUSHI ,  TANAKA TSUYOSHI

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/338 ,  H01L21/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/812

Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

公开(公告)号：JP2000294741A

公开(公告)日：2000-10-20

申请号：JP2000113468

申请日：2000-04-14

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NOMA JUNJI ,  UEDA DAISUKE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce the leakage current of a capacitor with a capacitance insulating film consisting of a ceramic thin film with perovskite structure, and to enhance a breakdown voltage. SOLUTION: On a foundation insulating film 12 being formed on a semiconductor substrate 11, a ferro-electric capacitor is formed, where the ferro-electric capacitor is composed of a lower electrode 13A, a ceramic capacitance film 14A consisting of a ferroelectric, and an upper electrode 15A. An interlayer insulation 16 is formed on the semiconductor substrate 11 so that the ferro- electric capacitor is covered, and electrode wiring 17 is formed on the interlayer insulation 16. A relationship of L>=2D is established between length L of the surface of the ceramic capacitance film 14A existing between the intersection of the side surface of the upper electrode 15A and the upper surface of the ceramic capacitance film 14A and the intersection of the side surface of the ceramic capacitance film 14A and the upper surface of the lower electrode 13A, and thickness D of the ceramic capacitance film 14A.

公开(公告)号：JPH0964060A

公开(公告)日：1997-03-07

申请号：JP24503895

申请日：1995-08-18

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ISHIDA HIDETOSHI ,  UEDA DAISUKE

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/861

Abstract: PROBLEM TO BE SOLVED: To suppress the decrease in the injection efficiency of minority carriers due to the generation of piezoelectric charge of a compound semiconductor device. SOLUTION: A cathode region 1 is provided on a compound semiconductor substrate 2 having the main surface of a plane (100). The flat surface shape of the region 1 is formed in a rectangular shape microminiaturized at the short side, and the direction of the long side of the rectangle is brought into coincidence with the direction [010] (or [001] direction) of the substrate 2. Since the generation of piezoelectric charge is suppressed in an anode region directly under the region 1 having such an orientation, the possibility of moving the carrier injected from the region 2 in the anode region to the surface region by piezoelectric charge to recombine at a surface level can be effectively reduced. The short side is microminiaturized to obtain the effect of reducing the parasitic capacity of a P-N junction. The structure can be applied to the case that the emitter region of the bipolar transistor is provided on a base region.

公开(公告)号：JPH08228138A

公开(公告)日：1996-09-03

申请号：JP32132895

申请日：1995-12-11

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MIYATSUJI KAZUO ,  UEDA DAISUKE

IPC: H03K17/687 ,  H03H11/24 ,  H03K17/00

Abstract: PURPOSE: To provide the semiconductor integrated circuit for high frequency for which power consumption and an occupied area are reduced, switchable power is enlarged, output generation distortion is reduced and peripheral circuits are simplified. CONSTITUTION: First and second signal terminals 6 and 7 are respectively connected to the drain and source of a field effect transistor(FET) and a first control terminal 3 is connected to its gate. Then, a first resistor member 2a is interposed between the gate and the first control terminal, and capacitors 5a and 5b are respectively interposed between the drain/source and the first/ second signal terminal. Besides, a second control terminal 4 is connected through a second resistor member 2b to one of drain and source at least. Then, a high frequency signal inputted to the first signal terminal 6 is passed through the FET and outputted from the second signal terminal 7 and the transmission amount of high frequency signal is controlled by a voltage signal for control inputted between the first and second control terminals 3 and 4.