公开(公告)号：US3442700A

公开(公告)日：1969-05-06

申请号：US3442700D

申请日：1966-12-23

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YOSHIOKA SATOSHI ,  TAKAYANAGI SHIGETOSHI

IPC: C01B33/18 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L23/29 ,  C23C13/04

CPC classification number: C23C16/45512 ,  B82Y30/00 ,  C01B33/183 ,  C01P2004/64 ,  C01P2004/86 ,  C01P2006/10 ,  C01P2006/60 ,  C23C16/402 ,  C23C16/45561 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：US3625749A

公开(公告)日：1971-12-07

申请号：US3625749D

申请日：1967-03-31

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YOSHIOKA SATOSHI ,  TAKAYANAGI SHIGETOSHI

IPC: C23C16/40 ,  C23C11/08 ,  C23C11/00

CPC classification number: C23C16/402

Abstract: An improved method for depositing silicon dioxide film on surfaces of substrates, which are stable at temperatures of 730* C. and above, by passing onto the surfaces thereof maintained at 730* C. or above, a gaseous hydrogen-carbon dioxide-silicon tetrafluoride mixture wherein the silicon tetrafluoride concentration is 0.005-0.1 percent by volume and the carbon dioxide concentration is 8 to 92 percent by volume. The film is useful for diffusion-masking films for selective diffusion in fabrication or for passivating films.

公开(公告)号：US3503798A

公开(公告)日：1970-03-31

申请号：US3503798D

申请日：1967-10-23

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YOSHIOKA SATOSHI ,  TAKAYANAGI SHIGETOSHI

IPC: C23C16/34 ,  H01L21/318 ,  B44D1/18

CPC classification number: H01L21/3185 ,  C23C16/345 ,  Y10S148/043

公开(公告)号：DE1521397A1

公开(公告)日：1969-07-03

申请号：DE1521397

申请日：1966-12-28

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YOSHIOKA SATOSHI ,  TAKAYANAGI SHIGETOSHI

IPC: C23C16/40 ,  H01L21/316 ,  C23C11/08

公开(公告)号：JPS5598843A

公开(公告)日：1980-07-28

申请号：JP498879

申请日：1979-01-20

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KANBARA GINJIROU ,  YOSHIOKA SATOSHI

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/331 ,  H01L29/73

Abstract: PURPOSE:To reduce the isolating area of isolating region for insulating and isolating a reverse conductivity type epitaxial layer grown on one conductivity type semiconductor substrate by forming a deep one conductivity region in the epiaxial layer between two shallow oxide layers formed in parallel in the isolating region when insulating and isolating the epitaxial layer. CONSTITUTION:When an n-type layer 2 is epitaxially grown on a p-type silicon substrate 1 and isolated in an island state using an insulating region, an SiO2 film 9 and an Si3N4 film 11 are first laminated on the layer 2. Then, two openings 12 and 13 are perforated at an interval on the region to be formed with an isolating region, and heat treated, thereby forming shallow oxide layers 14 and 15 in the layer 2 exposed through the openings 12 and 13. Thereafter, the films 11 and 9 of the region surrounded by the layers 14 and 15 are removed, and a p -type insulating region 17 is diffused in the portion 16 of the exposed layer 2, thereby isolating the layer 2 in an island state. Thus, the area required for insulating and isolating the layer 2 can be reduced, thereby obtaining an IC having high integrating degree.

公开(公告)号：JPS5547706A

公开(公告)日：1980-04-04

申请号：JP12102279

申请日：1979-09-20

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NANBU SHIYUUTAROU ,  NISHINO SEIJI ,  TAKAHASHI JIYUNICHI ,  TAKANORI TAKESHI ,  TSUDA ISAMU ,  YOSHIOKA SATOSHI

IPC: H03B9/12 ,  H03B9/14

Abstract: PURPOSE:To compensate the range of dispersion of oscillation frequency, by inserting conductive substance to the insulation package of solidstate oscillating element. CONSTITUTION:The conductive substance 5 is provided around the insulation package of solidstate oscillation element. The impedance of the solidstate element is increased by the share of the conductive substance 5. Accordingly, when the amount of the conductive substance 5 is increased, the reactive component is increased, the resonance frequency is lowered, and vice versa. As the conductive substance 5, the substance consisting of the dielectric substance 10 and metal 9 other than metal such as copper, gold, and aluminum, and the adjustment of frequency is easier since various impedances can be manufactured.

公开(公告)号：JPS5591846A

公开(公告)日：1980-07-11

申请号：JP16574678

申请日：1978-12-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： TAKANORI TAKESHI ,  YOSHIOKA SATOSHI

IPC: H01L23/12

Abstract: PURPOSE:To eliminate the mismatch between a transmission line on a printed circuit board and an external lead wire for input or output of a high-frequency IC by forming the lead wire in a belt-like shape wider than others. CONSTITUTION:Among external lead wires, an input lead wire 6 and an output lead wire 7 as an input terminal and output terminal of a high-frequency IC respectively are formed in a belt-like shape and drawn out at a right angle to other external lead wires 1. The external lead wires 6, 7 are led out of a sealed vessel and connected to microwave transmission lines on a printed circuit board with a good match. By so doing, as they are lead wires of belt shape, it is quite easy to connect them to the microwave transmission lines, while an unsuitable mismatching can be eliminated.

公开(公告)号：JPS5450284A

公开(公告)日：1979-04-20

申请号：JP11707877

申请日：1977-09-28

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YOSHIOKA SATOSHI

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205

Abstract: PURPOSE:To accurately form the electode wiring layers of fine patterns by using a rhodium film having high corrosion resistance for a mask in place of photo resist mask and etching barrier type metal films. CONSTITUTION:After an insulation film 2 in which Si3N4 film is the uppermost film is deposited on a Si substrate 1 having undergone diffusion process, openings 3 for electrode lead-out are etched. Next, a platinum silicide layer 4 is formed in said openings 3, after which a Ti film 5 and a Pt film 6 are deposited over the entire surface. A photo resist film 7 is nixt coated over the entire surface and is subjected to exposure and development to remove electrode wiring forming regions. Thereafter, a Rh film 8 is deposited through electrolytic plating on the exposed film 6 and the film 7 is removed. With the film 8 as a mask, the exposed film 6 is etched away by using mixed acids of aqua regia: acetic acid=1:1. Next, a thin insulation film of Ti compound is produced on the surface of the exposed film 5 by performing heat treatment in air, after which an Au film 9 is deposited on the film 8. After this, the substrate is dipped in sulfuric acid and hydrofluoric acid to remove the Ti compound and film 5, whereby the multilayer electrode wiring layers of required patterns are obtained.