公开(公告)号：FR2175960A1

公开(公告)日：1973-10-26

申请号：FR7308860

申请日：1973-03-13

Applicant: MATSUSHITA ELECTRONICS CORP ,  MATSUSHITA ELECTRONICS CORP JA

Inventor： ARITA SHIGERU

IPC: H01L23/535 ,  H01L27/07 ,  H01L21/82 ,  H01L27/112 ,  H01L29/00 ,  H01L7/64 ,  H01L11/14

公开(公告)号：FR2175819A1

公开(公告)日：1973-10-26

申请号：FR7308327

申请日：1973-03-08

Applicant: MATSUSHITA ELECTRONICS CORP ,  MATSUSHITA ELECTRONICS CORP JA

Inventor： ARITA SHIGERU

IPC: H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L21/82 ,  H01L29/00 ,  H01L19/00 ,  H01L11/14

公开(公告)号：FR2176825A1

公开(公告)日：1973-11-02

申请号：FR7309581

申请日：1973-03-16

Applicant: MATSUSHITA ELECTRONICS CORP ,  MATSUSHITA ELECTRONICS CORP JA

Inventor： ARITA SHIGERU

IPC: H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L21/82 ,  H01L29/00 ,  H01L19/00 ,  H01L7/00

公开(公告)号：FR2175961A1

公开(公告)日：1973-10-26

申请号：FR7308863

申请日：1973-03-13

Applicant: MATSUSHITA ELECTRONICS CORP ,  MATSUSHITA ELECTRONICS CORP JA

Inventor： ARITA SHIGERU

IPC: H01L23/535 ,  H01L27/07 ,  H01L21/82 ,  H01L27/112 ,  H01L29/00 ,  H01L7/64 ,  H01L11/14

公开(公告)号：US3865650A

公开(公告)日：1975-02-11

申请号：US34025473

申请日：1973-03-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L7/44 ,  B01J17/00 ,  H01L11/00

CPC classification number: H01L23/535 ,  H01L21/82 ,  H01L27/0733 ,  H01L27/112 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/053 ,  Y10S148/122 ,  H01L2924/00

Abstract: This invention relates to a method for manufacturing a MOS integrated circuit, especially to a method for connecting two regions in a MOS integrated circuit, wherein the connection is performed by means of a diffusion region formed prior to forming the gate portion and said diffusion region is a conductivity type opposite to that of a silicon substrate. According to the invention, it is not necessary to interconnect the two regions on the surface of the silicon substrate, so that a higher degree of integration will be attained as compared with the prior art.

Abstract translation: 本发明涉及一种用于制造MOS集成电路的方法，特别涉及一种用于连接MOS集成电路中的两个区域的方法，其中通过在形成栅极部分之前形成的扩散区域和所述扩散区域进行连接 与硅衬底相反的导电类型。 根据本发明，不需要将硅衬底的表面上的两个区域互连，从而与现有技术相比将获得更高的一体化度。

公开(公告)号：US3865651A

公开(公告)日：1975-02-11

申请号：US34025573

申请日：1973-03-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L7/44 ,  B01J17/00 ,  H01L27/10

CPC classification number: H01L23/535 ,  H01L21/82 ,  H01L27/0733 ,  H01L27/112 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/053 ,  Y10S148/122 ,  H01L2924/00

Abstract: An improved method of manufacturing series gate type matrix circuits by a self-alignment technique is provided. In this method, the drain and the source of a selected MOS field-effect transistor are short-circuited by a diffused region of a semiconductivity type opposite to that of a silicon substrate and formed prior to the formation of a gate portion. This method eliminates the use of interconnecting conductors for shortcircuiting the drains and the sources with the result that the surface area of the substrate which might have been occupied by such interconnecting conductors may be dispensed with to facilitate integration and moreover any desired matrix circuit may be formed by controlling conduction of such diffused regions.

Abstract translation: 提供了一种通过自对准技术制造串联栅极型矩阵电路的改进方法。 在这种方法中，所选择的MOS场效应晶体管的漏极和源极由与硅衬底相反的半导电性类型的扩散区域短路，并在形成栅极部分之前形成。 该方法消除了使用互连导体来短路漏极和源极，结果可以省去可能被这种互连导体占据的衬底的表面积，以便于集成，而且任何所需的矩阵电路可以 通过控制这种扩散区域的传导来形成。

公开(公告)号：US3874955A

公开(公告)日：1975-04-01

申请号：US34149373

申请日：1973-03-15

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L7/44 ,  B01J17/00 ,  H01L27/10

CPC classification number: H01L23/535 ,  H01L21/82 ,  H01L27/0733 ,  H01L27/112 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/053 ,  Y10S148/122 ,  H01L2924/00

Abstract: A method of manufacturing an MOS integrated circuit by utilizing a self-alignment technique is provided, wherein a capacitor is fabricated independently of other circuit elements. The capacitor is composed of a preliminary diffused region, a silicon dioxide layer and a gate electrode section having at least a portion thereof laid on top of the preliminary diffused region. The capacitor produced in accordance with this method is positively separated from other circuit elements and it may be used, for example, as an auxiliary storage capacitor for an inverter circuit to prevent the lowering of the output signal.

公开(公告)号：US3658610A

公开(公告)日：1972-04-25

申请号：US3658610D

申请日：1967-03-20

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU ,  KAMEI ICHIZO ,  OKUMURA TOMISABURO

IPC: H01L21/306 ,  C23F1/02 ,  H01L21/00 ,  H01L21/033 ,  H01L21/316 ,  H01L23/29 ,  H01L7/00 ,  H01L7/50

CPC classification number: H01L21/00 ,  C23F1/02 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/033 ,  H01L21/31662 ,  H01L23/293 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/106 ,  H01L2924/00

Abstract: A method of pattern-etching a passivation layer on the surface of a semiconductor body by means of the photoresist technique, said passivation layer consisting of laminated two layers, of which the solving speed of the upper layer in an etchant is higher than that of the lower layer; in which the lower layer is formed first, followed by etching into the desired pattern, the upper layer is next formed over the whole surface, then a photoresist film is applied in the identical pattern to the lower one, and finally the area or areas of the upper layer exposed at an opening or openings are etched away, whereby the defect that the upper layer having higher solubility is exclusively sideetched at the periphery of the pattern can be avoided.

Abstract translation: 通过光致抗蚀剂技术对半导体本体表面上的钝化层图案蚀刻的方法，所述钝化层由层压的两层组成，其中蚀刻剂中上层的求解速度高于 下层 其中首先形成下层，然后蚀刻成所需图案，然后在整个表面上形成上层，然后将光致抗蚀剂膜以相同的图案施加到下层，最后以 可以避免在开口或开口处露出的上层，从而可以避免在图案周边仅对侧面蚀刻具有较高溶解度的上层的缺陷。

公开(公告)号：GB1357515A

公开(公告)日：1974-06-26

申请号：GB1074073

申请日：1973-03-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L19/00 ,  H01L11/14

Abstract: 1357515 Semi-conductor devices MATSUSHITA ELECTRONICS CORP 6 March 1973 [10 March 1972] 10740/73 Heading H1K In a method of manufacturing a Si MOS integrated circuit in which the gate structure 2, 3 is used as a self-registering mask for diffusion of source and drain regions one pair of source and drain regions 4, 5 is interconnected by the earlier provision beneath the gate structure 2, 3 of a diffused region 9 of the same conductivity type as the regions 4, 5. The gate electrode 3 may be of Mo or polycrystalline Si.

公开(公告)号：DE2311913A1

公开(公告)日：1973-09-20

申请号：DE2311913

申请日：1973-03-09

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA SHIGERU

IPC: H01L21/82 ,  H01L23/535 ,  H01L27/07 ,  H01L27/112 ,  H01L29/00 ,  H01L7/34

Abstract: An improved method of manufacturing series gate type matrix circuits by a self-alignment technique is provided. In this method, the drain and the source of a selected MOS field-effect transistor are short-circuited by a diffused region of a semiconductivity type opposite to that of a silicon substrate and formed prior to the formation of a gate portion. This method eliminates the use of interconnecting conductors for short-circuiting the drains and the sources with the result that the surface area of the substrate which might have been occupied by such interconnecting conductors may be dispensed with to facilitate integration and moreover any desired matrix circuit may be formed by controlling conduction of such diffused regions.