公开(公告)号：CA2076666C

公开(公告)日：2000-06-27

申请号：CA2076666

申请日：1991-02-27

Applicant: MICRO TECHNOLOGY INC

Inventor： JAFFE DAVID H ,  POWERS DAVID T ,  GAJJAR KUMAR ,  GLIDER JOSEPH S ,  IDLEMAN THOMAS E

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/00 ,  G11B20/18

Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.

公开(公告)号：CA2076666A1

公开(公告)日：1991-09-03

申请号：CA2076666

申请日：1991-02-27

Applicant: MICRO TECHNOLOGY INC

Inventor： JAFFE DAVID H ,  POWERS DAVID T ,  GAJJAR KUMAR ,  GLIDER JOSEPH S ,  IDLEMAN THOMAS E

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/00 ,  G11B20/18

公开(公告)号：DE69128284D1

公开(公告)日：1998-01-08

申请号：DE69128284

申请日：1991-04-03

Applicant: MICRO TECHNOLOGY INC

Inventor： HENSON LARRY ,  GAJJAR KUMAR ,  POWERS DAVID ,  IDLEMAN THOMAS

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11B20/18 ,  H04J15/00

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

公开(公告)号：EP0532509A4

公开(公告)日：1994-05-11

申请号：EP91907296

申请日：1991-03-14

Applicant: MICRO TECHNOLOGY INC

Inventor： NGUYEN ANH ,  GAJJAR KUMAR

IPC: G06F3/06 ,  G06F13/12 ,  G06F13/00

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0691

Abstract: A data storage system having a local processor (28) and a plurality of memory storage elements (26) is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers (24), each coupled to a separate memory storage element (26). A data path control circuit (30) is programmed by the local processor (28) to control the transfer of data between the external CPUs and the memory buffers (24). Two interface circuits (16 and 18) are coupled between the external CPUs and the memory buffers (24) to provide two data paths for transferring data between the external CPUs and memory buffers (24). The data path control circuit (30) contains two independent sequencing circuits for selecting memory buffers (24). This allows one data path to be used for reading or writing to a number of the memory buffers (24) while the other data path is simultaneously used for a different operation for the rest of the memory buffers (24).