公开(公告)号：DE69128284D1

公开(公告)日：1998-01-08

申请号：DE69128284

申请日：1991-04-03

Applicant: MICRO TECHNOLOGY INC

Inventor： HENSON LARRY ,  GAJJAR KUMAR ,  POWERS DAVID ,  IDLEMAN THOMAS

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11B20/18 ,  H04J15/00

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.