公开(公告)号：JP2001229072A

公开(公告)日：2001-08-24

申请号：JP2001013888

申请日：2001-01-22

Applicant: MICROCHIP TECH INC

Inventor： DIPPENAAR THEODOR J ,  DUVENHAGE STEPHANUS P ,  MICHAEL S PISKA

IPC: G06F12/00 ,  G06F11/00 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To provide a memory storage architecture for preventing the generation of any time delay to arbitrary writing access in a memory. SOLUTION: This device is provided with a dual port device, a first device including an interrupting input, a first data bus, and a first address bus operationally connected to the dual port device, a second device including a second data bus and a second address bus operationally connected to the dual port device, and an address comparator operationally connected to the first address bus and the second address bus for generating a collision error signal according to a prescribed simultaneous access from the first and second devices to the dual device.