DIGITALLY SWITCHED POTENTIOMETER WITH IMPROVED LINEARITY AND SETTING TIME

    公开(公告)号:JP2001244816A

    公开(公告)日:2001-09-07

    申请号:JP2001017697

    申请日:2001-01-25

    Abstract: PROBLEM TO BE SOLVED: To provide a simple and economical digital potentiometer which has improved linearity and a shortened setting time when the resistance is changed by switching. SOLUTION: This potentiometer is equipped with plural 1st switches connected to a 1st input node, plural 2nd switched connected to a 2nd input node, plural 3rd switches connected to an output node, and 1st, 2nd, and 3rd strings of series-connected resistors; and the 1st string is connected between the 1st string and 2nd string, the 1st switches between the 1st input node and the 1st string of the resistors, the 2nd switches between the 2nd input node and the 2nd string of the resistors, and the 3rd switches between the output node and the 3rd string of the resistors.

    Digitally switched impedance having improved linearity and settling time

    公开(公告)号:AU2002306678A1

    公开(公告)日:2002-09-24

    申请号:AU2002306678

    申请日:2002-03-11

    Abstract: A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

    DIGITALLY SWITCHED IMPEDANCE HAVING IMPROVED LINEARITY AND SETTLING TIME
    3.
    发明申请
    DIGITALLY SWITCHED IMPEDANCE HAVING IMPROVED LINEARITY AND SETTLING TIME 审中-公开
    具有改进的线性和稳定时间的数字切换阻抗

    公开(公告)号:WO02073796A2

    公开(公告)日:2002-09-19

    申请号:PCT/US0207118

    申请日:2002-03-11

    CPC classification number: H03M1/682 H03M1/765

    Abstract: A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

    Abstract translation: 通过最小化由用于切换包括数字切换阻抗的阻抗元件的开关引起的阻抗误差的量,数字开关阻抗具有改善的线性度。 通过减少连接到数字开关阻抗的输出的开关电容量,可以实现数字开关阻抗的改善建立时间。 数字开关阻抗可以制造在集成电路管芯上,并且开关可以用互补金属氧化物半导体(CMOS)晶体管制造。 通过使用两个主要阻抗等级和一个次要阻抗等级,或两个次要阻抗等级和一个主要阻抗等级串联连接,减少所需数量的阻抗阶跃变化所需的阻抗数量。

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