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    A METHOD OF CHECKING EEPROM DATA WITH AN EMBEDDED CRC
    3.
    发明申请
    A METHOD OF CHECKING EEPROM DATA WITH AN EMBEDDED CRC 审中-公开
    使用嵌入式CRC检查EEPROM数据的方法

    公开(公告)号：WO0198872A2

    公开(公告)日：2001-12-27

    申请号：PCT/US0141063

    申请日：2001-06-20

    Applicant: MICROCHIP TECH INC

    Inventor： ALEXANDER SAMUEL E ,  SALESKY RONALD D

    IPC: G06F11/10 ,  G06F12/16 ,  H03M13/09 ,  G06F

    CPC classification number: G06F11/1004

    Abstract: A method and apparatus for determining the integrity of data stored in a PROM device provides at least one holding latch connected to two sets of blocks. The first set of blocks contains data. The second set of blocks contains CRC information corresponding to the data in the first set of blocks. Upon reading the data from a first data block, the CRC information from the corresponding CRC block is also read. The data read is applied to the CRC algorithm to generate a current CRC value. The current CRC value is then compared to the CRC information obtained from the corresponding CRC block. The two CRC values are identical, the data is considered valid. Otherwise, the data is considered invalid.

    Abstract translation: 用于确定存储在PROM装置中的数据的完整性的方法和装置提供连接到两组块的至少一个保持锁存器。 第一组块包含数据。 第二组块包含与第一组块中的数据相对应的CRC信息。 在从第一数据块读取数据时，也读取来自相应的CRC块的CRC信息。 将数据读取应用于CRC算法以产生当前CRC值。 然后将当前CRC值与从对应的CRC块获得的CRC信息进行比较。 两个CRC值相同，数据被认为是有效的。 否则，数据被视为无效。

    METHOD, SYSTEM AND APPARATUS FOR CALIBRATING A PULSE POSITION MODULATION (PPM) DECODER TO A PPM SIGNAL
    4.
    发明申请
    METHOD, SYSTEM AND APPARATUS FOR CALIBRATING A PULSE POSITION MODULATION (PPM) DECODER TO A PPM SIGNAL 审中-公开
    用于将脉冲位置调制（PPM）解码器校准到PPM信号的方法，系统和装置

    公开(公告)号：WO0201246A3

    公开(公告)日：2002-04-04

    申请号：PCT/US0119599

    申请日：2001-06-20

    Applicant: MICROCHIP TECH INC

    Inventor： ALEXANDER SAMUEL E ,  LOYER STEPHEN R

    IPC: G01S13/78 ,  G01S13/76 ,  G06K19/07 ,  H04B14/02 ,  G01S13/02

    CPC classification number: G06K19/0723 ,  G01S13/76 ,  H04B14/026

    Abstract: A radio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an internal oscillator of the RFID tag device and an external PPM source such as a RFID tag reader. The PPM decoder circuit is calibrated to the difference between the external PPM frequency source (i.e., RFID tag reader) and the internal clock-oscillator of the RFID tag device, which is performed in a single measurement during one calibration symbol period.

    Abstract translation: 一种射频识别（RFID）标签装置，具有脉冲位置调制（PPM）解码器电路，其计算RFID标签装置的内部振荡器和诸如RFID标签读取器的外部PPM源之间的相对频率关系。 PPM解码器电路被校准为外部PPM频率源（即，RFID标签读取器）与RFID标签装置的内部时钟振荡器之间的差异，其在一个校准符号周期期间在单个测量中执行​​。

    6.
    发明专利
    未知

    公开(公告)号：DK0715736T3

    公开(公告)日：2001-01-02

    申请号：DK95924675

    申请日：1995-06-22

    Applicant: MICROCHIP TECH INC

    Inventor： ALEXANDER SAMUEL E

    IPC: G11C17/00 ,  G06F13/38 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C7/00 ,  G06F1/10 ,  G06F1/12

    Abstract: An I2C bus-compatible, serial EEPROM device is used in applications involving storage and serial transmission of configuration and control information for an intelligent peripheral device with which the EEPROM device is associated, for communication on a bus to a host device adapted to control the peripheral device. The EEPROM device has a memory array for storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device, and are alternately and selectively established according to whether data stored in the EEPROM array is to be read only, by sequential output onto the bus, or the array is also to be allowed to be written to. The arrangement ultimately allows intelligent interaction between the host device and the peripheral device. A separate clock line supplements the usual clock line and data line of an I2C bus to support the distinct and different modes, with clocking by the respective clock line for the established mode. A controlled multiplexer selectively connects the input clock according to a predetermined logic level transition on one of the two clock lines.

    MEMORY DEVICE WITH SWITCHING OF DATA STREAM MODES
    7.
    发明公开
    MEMORY DEVICE WITH SWITCHING OF DATA STREAM MODES 失效
    SPEICHERVORRICHTUNG MIT DER SCHALTUNG VON DATENSTROMBETRIEBSARTEN

    公开(公告)号：EP0715736A4

    公开(公告)日：1996-12-27

    申请号：EP95924675

    申请日：1995-06-22

    Applicant: MICROCHIP TECH INC

    Inventor： ALEXANDER SAMUEL E

    IPC: G11C17/00 ,  G06F13/38 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G06F1/10 ,  G06F1/12

    CPC classification number: G11C7/1072

    Abstract: I C bus-compatible, serial EEPROM device (10) is used in applications involving storage and serial transmission of configuration and control information for an associated intelligent peripheral device communicating on a bus to a host device. The EEPROM device (10) has a memory array (20) storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device (10), and are alternately and selectively established according to whether data stored in EEPROM array is to be accessed read only or read/write. The arrangement allows intelligent interaction between the host and the peripheral device. Multiplexer (35) selectively connects the input clock, comprising either the usual input clock line to the bus or a separate clock line, for clocking the different modes according to a predetermined logic level transition on one of the two clock lines.

    Abstract translation: I2C总线兼容的串行EEPROM器件（10）用于涉及用于在总线上向主机设备通信的相关联的智能外围设备的配置和控制信息的存储和串行传输的应用。 EEPROM器件（10）具有存储表示配置和控制信息的数据的存储器阵列（20）。 EEPROM器件（10）支持两种数据传输模式，并根据存储在EEPROM阵列中的数据是只读还是读/写来交替选择建立。 该布置允许主机和外围设备之间的智能交互。 多路复用器（35）选择性地连接输入时钟，该输入时钟包括通向总线的通用输入时钟线或单独的时钟线，用于根据两条时钟线之一上的预定逻辑电平转换为不同模式提供时钟。

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