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1.发明申请
公开(公告)号：WO1997044905A1
公开(公告)日：1997-11-27
申请号：PCT/US1997008186
申请日：1997-05-21
Applicant: MICROCHIP TECHNOLOGY, INC.
Inventor： MICROCHIP TECHNOLOGY, INC. , HULL, Richard, L. , BINGHAM, Gregory , FINK, Scott , ROGERS, James, Clark , ELLISON, Scott
IPC: H03L07/00
CPC classification number: G06F15/7814
Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external component. The microcontroller can function in a proper manner from the application of only power and signal lines with no external component required. The microcontroller (10) has integrated internal reset (14) and oscillator (16) circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors into the microcontroller.
Abstract translation: 本发明涉及一种微控制器，其可被配置为在没有任何外部部件的伴随的情况下运行。 只有电源和信号线的应用，微控制器才能正常工作，无需外部元件。 微控制器（10）将内部复位（14）和振荡器（16）电路集成到微控制器中。 微控制器还将简单的外部元件（如限流电阻）集成到微控制器中。
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2.发明申请
公开(公告)号：WO1997044904A1
公开(公告)日：1997-11-27
申请号：PCT/US1997008185
申请日：1997-05-21
Applicant: MICROCHIP TECHNOLOGY, INC.
Inventor： MICROCHIP TECHNOLOGY, INC. , HULL, Richard, L. , BINGHAM, Gregory
IPC: H03L07/00
CPC classification number: H03K17/164 , G06F1/08 , G06F15/7814 , H03K3/0231 , Y02D10/12 , Y02D10/13
Abstract: A microcontroller circuit (10) includes an oscillator (14) receiving frequency trimming data (28) from a memory (16) under control of a microcontroller logic (12). The microcontroller logic (12) permits a user to alter the trimming data and to select through an oscillator logic (20) either the oscillator (14) or an external oscillator source (34) as a system clock (32).
Abstract translation: 微控制器电路（10）包括在微控制器逻辑（12）的控制下从存储器（16）接收频率修整数据（28）的振荡器（14）。 微控制器逻辑（12）允许用户改变修整数据并通过振荡器逻辑（20）选择振荡器（14）或外部振荡器源（34）作为系统时钟（32）。
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公开(公告)号：WO1997045958A1
公开(公告)日：1997-12-04
申请号：PCT/US1997006483
申请日：1997-04-12
Applicant: MICROCHIP TECHNOLOGY, INC.
Inventor： MICROCHIP TECHNOLOGY, INC. , HULL, Richard, L. , ELLISON, Scott
IPC: H03K19/0175
CPC classification number: H03K19/01759
Abstract: The invention relates to a configurable IC device pin (14), which may be either a device clock input pin or a digital I/O pin in one embodiment, or a reset pin or a digital I/O pin in another embodiment. Both embodiments use a memory device (16) to store configuration data for the pin. Input/output logic (18) is also used in both embodiments to transfer data to and from the IC pin (14) when configured as a digital I/O pin.
Abstract translation: 本发明涉及一种可配置IC器件引脚（14），其可以是一个实施例中的器件时钟输入引脚或数字I / O引脚，或者另一实施例中的复位引脚或数字I / O引脚。 两个实施例都使用存储器件（16）来存储引脚的配置数据。 当配置为数字I / O引脚时，两个实施例中还使用输入/输出逻辑（18）来将数据传送到IC引脚（14）。
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4.发明申请
公开(公告)号：WO1997045959A1
公开(公告)日：1997-12-04
申请号：PCT/US1997006482
申请日：1997-04-12
Applicant: MICROCHIP TECHNOLOGY, INC.
Inventor： MICROCHIP TECHNOLOGY, INC. , HULL, Richard, L. , BINGHAM, Gregory , FINK, Scott , ROGERS, James, Clark , ELLISON, Scott
IPC: H03L07/00
CPC classification number: H03K17/164 , G06F1/08 , G06F15/7814 , H03K3/0231 , Y02D10/12 , Y02D10/13
Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external components. The microcontroller can function in a proper manner from the application of only power and signal lines with no external components required. The microcontroller (10) has integrated internal reset (14) and oscillator (16) circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors and pull up and pull down resistors into the microcontroller in order to avoid application specific external components.
Abstract translation: 本发明涉及一种微控制器，其可被配置为在没有任何外部部件的伴随的情况下运行。 微控制器可以以适当的方式运行，仅应用电源和信号线，无需外部元件。 微控制器（10）将内部复位（14）和振荡器（16）电路集成到微控制器中。 微控制器还集成了简单的外部组件，例如限流电阻，并将电阻上拉和下拉到微控制器中，以避免应用特定的外部组件。
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公开(公告)号：EP0787379A1
公开(公告)日：1997-08-06
申请号：EP96924422.0
申请日：1996-07-17
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： YACH, Randy, L. , HULL, Richard, L.
CPC classification number: H03K17/223 , G11C5/143 , H02H3/243 , H03K17/145 , H03K17/22
Abstract: A power-on reset circuit (10) for resetting electronic circuitry to be monitored has been provided. The power-on reset circuit includes a trip point generator (12) including the worst case component (the component that requires the greatest power supply voltage to operate) within the electronic circuitry for setting the threshold voltatge for taking the electronic circuitry out of reset such that if the worst case component is operative, it is guaranteed that all components are operative and, thus, the electronic circuitry can be taken out of reset. Moreover, because the threshold voltage is based upon the worst case component of the electronic circuitry, the threshold voltage of the trip point generator will adequately track the electronic circuitry over normal process and temperature variations. Additionally, the power-on reset circuit includes a noise filter (34) for placing the electronic circuitry back into reset if variations within the power supply voltage cause the power supply voltage level to fall below a predetermined threshold for at least a minimum period of time.
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Patent Agency Ranking
公开(公告)号：EP0864156A1
公开(公告)日：1998-09-16
申请号：EP97943476.0
申请日：1997-09-25
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： HULL, Richard, L. , YACH, Randy, L.
IPC: G11C16
Abstract: A technique for reading data from a selected memory element (25) of an EPROM array having rows (28) and columns (30) with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element (25) includes a transistor having gate (27), source (29), and drain (30) electrodes, and after selection of a particular element from which data is to be read by appropriately biasing the row and column associated with that memory element, the source (29) electrode thereof is selectively connected to ground by a switching element (33) to allow current flow through the source-drain path of the memory element and enable the read out of data therefrom after the drain and gate voltages of the memory element (25) have been stabilized.
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公开(公告)号：EP0864203A1
公开(公告)日：1998-09-16
申请号：EP97943473.0
申请日：1997-09-25
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： HULL, Richard, L. , YACH, Randy, L.
CPC classification number: H03K3/356113 , H03K17/102
Abstract: A voltage level shifting complementary metal-oxide-silicon (CMOS) buffer (30-47) is arranged and configured to operate in two distinct modes - one of which is high voltage and the other low voltage - depending on the level of the supply voltage (40) to the buffer relative to the operating voltage (VDD) of a device in which the buffer is integrated. In the high voltage mode, in which the supply voltage level exceeds the operating voltage level, the buffer is constrained to perform as a high voltage level shifter. In the low voltage mode, in which the supply voltage level is equal to or less than the operating voltage level, the buffer is constrained to perform as a CMOS logic gate.
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公开(公告)号：EP0864154A1
公开(公告)日：1998-09-16
申请号：EP97943474.0
申请日：1997-09-25
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： HULL, Richard, L. , YACH, Randy, L.
IPC: G11C16
CPC classification number: G11C16/26
Abstract: A method of high speed reading of data from an EPROM, in which a memory array (12) is programmed based on device status at intersections of rows and columns of the array to store data therein as 0's and 1's, uses a capacitive overcharging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing memory element (25) to be read is quickly overdriven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage (Vdd) which may exceed the programmed threshold voltage of the selected memory element (25). The effective capacitance is thereupon discharged to voltage level below both the maximum level of the supply voltage (Vdd) and the programmed threshold. Then the status and data content of the selected memory element (25) are read by first grounding an electrode of a source-drain path of the transistor comprising the memory element (25) to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier (17) in source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element (25).
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公开(公告)号：EP0840956B1
公开(公告)日：2004-01-28
申请号：EP97926507.1
申请日：1997-05-21
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： HULL, Richard, L. , BINGHAM, Gregory , FINK, Scott , ROGERS, James, Clark , ELLISON, Scott
CPC classification number: G06F15/7814
Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external component. The microcontroller can function in a proper manner from the application of only power and signal lines with no external component required. The microcontroller (10) has integrated internal reset (14) and oscillator (16) circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors into the microcontroller.
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公开(公告)号：EP0864155A1
公开(公告)日：1998-09-16
申请号：EP97943475.0
申请日：1997-09-25
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： HULL, Richard, L. , YACH, Randy, L.
Abstract: A technique is disclosed for reading a memory element (25) of an EPROM array (12) embedded in a microcontroller chip (10) which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabricating the chip. The microcontroller chip (10) has a predetermined supply voltage (40), and the array (12) comprises rows and columns of addressable memory elements (12) which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage (Vref) is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage (Vdd), and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.
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