公开(公告)号：WO1993010493A1

公开(公告)日：1993-05-27

申请号：PCT/US1992009463

申请日：1992-11-12

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： MICROCHIP TECHNOLOGY INC. ,  YACH, Randy, L. ,  MITRA, Sumit

IPC: G06F11/00

CPC classification number: G06F1/24 ,  G06F11/221

Abstract: A microcontroller (10) is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller (10) includes a power supply (70, 85) for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller (10) is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply (70, 85) is in a predetermined range and the clock frequency supplied by the clock is stable.

Abstract translation: 微控制器（10）在操作时适于执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。 微控制器（10）包括用于在适合于其操作的预定范围内向整个装置供电的电源（70,85）和用于向微控制器提供时钟频率的时钟，其具有适于精确定时和计数的稳定性 在设备内。 微控制器（10）被选择性地复位以防止它执行用于产生控制信号的程序和指令，并且尽管开始从复位状态移除直到电源提供的电力 70,85）处于预定范围，并且由时钟提供的时钟频率是稳定的。

公开(公告)号：EP1090425A1

公开(公告)日：2001-04-11

申请号：EP00918141.3

申请日：2000-03-17

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GERBER, Donald, S. ,  YACH, Randy, L. ,  HEWITT, Kent, D. ,  SPADINI, Gianpaolo

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  H01L27/0207 ,  H01L27/11519

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

公开(公告)号：EP0787379A1

公开(公告)日：1997-08-06

申请号：EP96924422.0

申请日：1996-07-17

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： YACH, Randy, L. ,  HULL, Richard, L.

IPC: G11C5 ,  H02H3 ,  H02J1 ,  H03K17

CPC classification number: H03K17/223 ,  G11C5/143 ,  H02H3/243 ,  H03K17/145 ,  H03K17/22

Abstract: A power-on reset circuit (10) for resetting electronic circuitry to be monitored has been provided. The power-on reset circuit includes a trip point generator (12) including the worst case component (the component that requires the greatest power supply voltage to operate) within the electronic circuitry for setting the threshold voltatge for taking the electronic circuitry out of reset such that if the worst case component is operative, it is guaranteed that all components are operative and, thus, the electronic circuitry can be taken out of reset. Moreover, because the threshold voltage is based upon the worst case component of the electronic circuitry, the threshold voltage of the trip point generator will adequately track the electronic circuitry over normal process and temperature variations. Additionally, the power-on reset circuit includes a noise filter (34) for placing the electronic circuitry back into reset if variations within the power supply voltage cause the power supply voltage level to fall below a predetermined threshold for at least a minimum period of time.

公开(公告)号：EP1066651A2

公开(公告)日：2001-01-10

申请号：EP99965330.6

申请日：1999-12-20

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： YACH, Randy, L. ,  WOJEWODA, Igor

IPC: H01L27/08 ,  H01L29/92

CPC classification number: H01L27/0805

Abstract: A matching capacitor array is implemented on a single, monolithic integrated circuit. The array fastures a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

公开(公告)号：EP0864155A1

公开(公告)日：1998-09-16

申请号：EP97943475.0

申请日：1997-09-25

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： HULL, Richard, L. ,  YACH, Randy, L.

IPC: G11C16 ,  G11C5

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A technique is disclosed for reading a memory element (25) of an EPROM array (12) embedded in a microcontroller chip (10) which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabricating the chip. The microcontroller chip (10) has a predetermined supply voltage (40), and the array (12) comprises rows and columns of addressable memory elements (12) which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage (Vref) is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage (Vdd), and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.

公开(公告)号：EP1090425B1

公开(公告)日：2012-06-27

申请号：EP00918141.3

申请日：2000-03-17

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GERBER, Donald, S. ,  YACH, Randy, L. ,  HEWITT, Kent, D. ,  SPADINI, Gianpaolo

IPC: H01L27/115 ,  H01L21/8247 ,  G11C16/04 ,  H01L27/02

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  H01L27/0207 ,  H01L27/11519

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

公开(公告)号：EP0864203A1

公开(公告)日：1998-09-16

申请号：EP97943473.0

申请日：1997-09-25

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： HULL, Richard, L. ,  YACH, Randy, L.

IPC: G11C16 ,  H03K3 ,  H03K17 ,  H03K19

CPC classification number: H03K3/356113 ,  H03K17/102

Abstract: A voltage level shifting complementary metal-oxide-silicon (CMOS) buffer (30-47) is arranged and configured to operate in two distinct modes - one of which is high voltage and the other low voltage - depending on the level of the supply voltage (40) to the buffer relative to the operating voltage (VDD) of a device in which the buffer is integrated. In the high voltage mode, in which the supply voltage level exceeds the operating voltage level, the buffer is constrained to perform as a high voltage level shifter. In the low voltage mode, in which the supply voltage level is equal to or less than the operating voltage level, the buffer is constrained to perform as a CMOS logic gate.

公开(公告)号：EP0864154A1

公开(公告)日：1998-09-16

申请号：EP97943474.0

申请日：1997-09-25

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： HULL, Richard, L. ,  YACH, Randy, L.

IPC: G11C16

CPC classification number: G11C16/26

Abstract: A method of high speed reading of data from an EPROM, in which a memory array (12) is programmed based on device status at intersections of rows and columns of the array to store data therein as 0's and 1's, uses a capacitive overcharging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing memory element (25) to be read is quickly overdriven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage (Vdd) which may exceed the programmed threshold voltage of the selected memory element (25). The effective capacitance is thereupon discharged to voltage level below both the maximum level of the supply voltage (Vdd) and the programmed threshold. Then the status and data content of the selected memory element (25) are read by first grounding an electrode of a source-drain path of the transistor comprising the memory element (25) to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier (17) in source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element (25).

公开(公告)号：EP0864156A1

公开(公告)日：1998-09-16

申请号：EP97943476.0

申请日：1997-09-25

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： HULL, Richard, L. ,  YACH, Randy, L.

IPC: G11C16

CPC classification number: G11C16/26 ,  G11C16/30

Abstract: A technique for reading data from a selected memory element (25) of an EPROM array having rows (28) and columns (30) with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element (25) includes a transistor having gate (27), source (29), and drain (30) electrodes, and after selection of a particular element from which data is to be read by appropriately biasing the row and column associated with that memory element, the source (29) electrode thereof is selectively connected to ground by a switching element (33) to allow current flow through the source-drain path of the memory element and enable the read out of data therefrom after the drain and gate voltages of the memory element (25) have been stabilized.

公开(公告)号：EP0864155B1

公开(公告)日：2003-05-21

申请号：EP97943475.0

申请日：1997-09-25

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： HULL, Richard, L. ,  YACH, Randy, L.

IPC: G11C16/26 ,  G11C16/08 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A technique is disclosed for reading a memory element (25) of an EPROM array (12) embedded in a microcontroller chip (10) which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabricating the chip. The microcontroller chip (10) has a predetermined supply voltage (40), and the array (12) comprises rows and columns of addressable memory elements (12) which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage (Vref) is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage (Vdd), and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.