公开(公告)号：WO1996012301A1

公开(公告)日：1996-04-25

申请号：PCT/US1995012767

申请日：1995-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  DENNISON, Charles, H. ,  AHMAD, Aftab

IPC: H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/8238 ,  H01L27/105

Abstract: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch. Thus, a low-aspect-ratio etch can be employed to pattern P-channel devices, and a blanket P+ implant may be performed without implanting the P-type impurity into source/drain regions of the N-channel devices. Another important feature of the invention is the incorporation of P-channel gate sidewall spacers and offset P-channel implants into the process flow.

Abstract translation: 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 本发明的重点是CMOS制造工艺流程，其允许电容器形成之后的P沟道源极/漏极掺杂。 该工艺的主要特征是在N沟道器件图案化之后，但在P沟道器件图案化之前，沉积和平坦化厚的绝缘模具层。 在该过程的一个实施例中，在存储节点接触蚀刻期间，去除覆盖在P沟道晶体管区域上的该绝缘层的部分。 因此，可以采用低纵横比蚀刻图案P沟道器件，并且可以执行覆盖P +注入而不将P型杂质注入到N沟道器件的源极/漏极区域中。 本发明的另一个重要特征是将P沟道栅极侧壁间隔物和偏移P沟道植入物结合到工艺流程中。