公开(公告)号：WO1991013392A2

公开(公告)日：1991-09-05

申请号：PCT/US1991000987

申请日：1991-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HESSON, James

IPC: G06F07/50

CPC classification number: G06F7/501 ,  G06F2207/3876 ,  H03K19/09429 ,  H03K19/1736

Abstract: Fast CMOS fully differential logic circuitry, using only tristatable buffers, and capable of as low as a single transistor propagation delay. The preferred embodiment of the invention includes four tristatable buffers (A1, A2, A3, and A4) connected together in such a way as to have multiple differential inputs and one differential output. Different configurations of the output and inputs make different logic functions available. An alternate embodiment combines three of these logic circuits to make a fully differential 3-input full adder, generating sum (SUM/SUM*) and carry outputs (COUT/COUT*) within two transistor delays.

Abstract translation: 快速CMOS全差分逻辑电路，仅使用可调缓冲器，并且能够低至单个晶体管传播延迟。 本发明的优选实施例包括以能够具有多个差分输入和一个差分输出的方式连接在一起的四个可跟踪缓冲器（A1，A2，A3和A4）。 输出和输入的不同配置使不同的逻辑功能可用。 一个替代实施例组合了这三个逻辑电路以产生全差分3输入全加器，产生和（SUM / SUM *）并且在两个晶体管延迟之内传送输出（COUT / COUT *）。