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    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    1.
    发明申请
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：WO2019103769A1

    公开(公告)日：2019-05-31

    申请号：PCT/US2018/044434

    申请日：2018-07-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G11C7/10 ,  G11C7/22

    Abstract: Methods, systems, and apparatuses related to memory operation with on- die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion ( e.g. , rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

    DISTRIBUTED MODE REGISTERS IN MEMORY DEVICES
    2.
    发明申请
    DISTRIBUTED MODE REGISTERS IN MEMORY DEVICES 审中-公开

    公开(公告)号：WO2019045795A1

    公开(公告)日：2019-03-07

    申请号：PCT/US2018/029143

    申请日：2018-04-24

    Applicant: MICRON TECHNOLOGY, INC

    Inventor： MAI, Thanh K. ,  HOWE, Gary

    IPC: G11C7/10 ,  G11C8/12

    Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

    COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION
    4.
    发明申请
    COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION 审中-公开

    公开(公告)号：WO2019045792A1

    公开(公告)日：2019-03-07

    申请号：PCT/US2018/028892

    申请日：2018-04-23

    Applicant: MICRON TECHNOLOGY, INC

    Inventor： HOWE, Gary

    IPC: G11C7/10

    Abstract: A memory device (10) may include one or more memory banks (12) that store data and one or more input buffers (50). The input buffers (50) may receive command address signals to access the one or more memory banks (12). The memory device (10) may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers (50) may operate under a first bias current when the memory device (10) is in the first mode of operation or a second bias current when the memory device (10) is in the second mode of operation, and the first bias current may be greater than the second bias current.

    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    5.
    发明公开
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：EP4446899A3

    公开(公告)日：2024-12-11

    申请号：EP24198261.0

    申请日：2018-07-30

    Applicant: Micron Technology, Inc.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G06F13/40

    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    7.
    发明公开
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：EP4446899A2

    公开(公告)日：2024-10-16

    申请号：EP24198261.0

    申请日：2018-07-30

    Applicant: Micron Technology, Inc.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G06F13/40

    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

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