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    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    1.
    发明申请
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：WO2019103769A1

    公开(公告)日：2019-05-31

    申请号：PCT/US2018/044434

    申请日：2018-07-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G11C7/10 ,  G11C7/22

    Abstract: Methods, systems, and apparatuses related to memory operation with on- die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion ( e.g. , rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

    MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE
    2.
    发明申请
    MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE 审中-公开
    用于半导体器件的多层引线框架

    公开(公告)号：WO1996015555A1

    公开(公告)日：1996-05-23

    申请号：PCT/US1995014569

    申请日：1995-11-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  STAVE, Eric, J.

    IPC: H01L23/495

    CPC classification number: H01L23/49589 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A multi-layer lead frame (20) for decoupling a power supply to a semiconductor die (10) includes overlaying first (25) and second lead frame (40) bodies having an insulator (55) disposed therebetween and at least one main lead finger (35, 50) extending from each body (25, 40). The bodies (25, 40) act as a capacitor to decouple the power supply to the die (10). One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die (10), and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die (10). The first body (25) includes a die paddle (30) for supporting the die (10), and the second body (40) includes a plate (45) for overlaying the paddle (30) with the insulator (55) disposed between the paddle (30) and plate (45), thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

    Abstract translation: 用于将电源去耦合到半导体管芯（10）的多层引线框架（20）包括覆盖第一（25）和第二引线框架（40）的主体，绝缘体（55）设置在它们之间，并且至少一个主引线指 （35,50），其从每个主体（25,40）延伸。 主体（25,40）用作电容器以将电源分离到管芯（10）。 主体和相应手指中的一个提供用于与模具（10）引线接合的电源和接地连接之一，并且另一个主体提供用于与模具（10）引线接合的另一个电源和接地连接。 第一主体（25）包括用于支撑模具（10）的模板（30），并且第二主体（40）包括用于将桨叶（30）与绝缘体（55）重叠的板（45） 叶片（30）和板（45），从而在分别提供电源和接地连接时在其间提供电去耦效应。

    VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS
    3.
    发明申请
    VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS 审中-公开

    公开(公告)号：WO2021158522A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/016176

    申请日：2021-02-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： HOLLIS, Timothy, M. ,  REHMEYER, James, S. ,  CHOI, Baekkyu ,  SHARMA, Yogesh ,  STAVE, Eric, J. ,  HUBER, Brian, W. ,  WISCOMBE, Miles, S.

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G06F3/06

    Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    5.
    发明公开
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：EP4446899A3

    公开(公告)日：2024-12-11

    申请号：EP24198261.0

    申请日：2018-07-30

    Applicant: Micron Technology, Inc.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G06F13/40

    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    8.
    发明公开
    METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：EP4446899A2

    公开(公告)日：2024-10-16

    申请号：EP24198261.0

    申请日：2018-07-30

    Applicant: Micron Technology, Inc.

    Inventor： HOWE, Gary ,  STAVE, Eric, J. ,  KINSLEY, Thomas, H. ,  PRATHER, Matthew, A.

    IPC: G06F13/40

    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

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