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    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING
    1.
    发明申请
    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING 审中-公开
    具有不对称电荷捕获的多状态存储单元

    公开(公告)号：WO2005083797A1

    公开(公告)日：2005-09-09

    申请号：PCT/US2005/004765

    申请日：2005-02-15

    Applicant: MICRON TECHNOLOGY, INC. ,  PRALL, Kirk

    Inventor： PRALL, Kirk

    IPC: H01L29/792

    CPC classification number: H01L29/7887 ,  H01L29/7923

    Abstract: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide - nitride - oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide - nitride - oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

    Abstract translation: 多态NAND存储单元由衬底中的两个漏极/源极区域组成。 在漏极/源极区域之间的衬底上方形成氧化物 - 氮化物 - 氧化物结构。 用作不对称电荷捕获层的氮化物层。 控制栅极位于氧化物 - 氮化物 - 氧化物结构之上。 在漏极/源极区域上的不对称偏置导致具有较高电压的漏极/源极区域通过栅极感应漏极漏极注入到基本上邻近该漏极/源极区域的俘获层而注入不对称分布孔。

    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AN METHODS
    2.
    发明申请
    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AN METHODS 审中-公开
    NROM存储单元，存储器阵列，相关设备方法

    公开(公告)号：WO2004001802A2

    公开(公告)日：2003-12-31

    申请号：PCT/US2003/019303

    申请日：2003-06-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： PRALL, Kirk ,  FORBES, Leonard

    IPC: H01L

    CPC classification number: H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

    Abstract: An array of memory cells configured to store at least one bit per one F 2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vtl) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

    Abstract translation: 配置为存储每个F 2至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷电平中的一个，该栅极绝缘体与第一源极/漏极区相邻，使得沟道区具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。

    A 2F2 MEMORY DEVICE SYSTEM AND METHOD
    3.
    发明申请
    A 2F2 MEMORY DEVICE SYSTEM AND METHOD 审中-公开
    2F 2存储器件系统和方法

    公开(公告)号：WO2002073698A2

    公开(公告)日：2002-09-19

    申请号：PCT/US2002/005716

    申请日：2002-02-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： PRALL, Kirk

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/7883

    Abstract: Methods and devices are disclosed which provide for memory devices having reduced memory cell square feature sizes. Such square feature sizes can permit large memory devices, on the order of a gigabyte or large, to be fabricated on one chip or die. The methods and devices disclosed, along with variations of them, utilize three dimensions as opposed to other memory devices which are fabricated in only two dimensions. Thus, the methods and devices disclosed , along with variations, contains substantially horizontal and vertical components.

    Abstract translation: 公开了提供具有减小的存储单元方形特征尺寸的存储器件的方法和装置。 这样的方形特征尺寸可以允许在一个芯片或芯片上制造大约十亿字节或大的大型存储器件。 所公开的方法和装置以及它们的变型利用三维而不是仅在二维制造的其它存储器件。 因此，所公开的方法和装置连同变型包含基本水平和垂直的部件。

    MEMORY CELL IMPRINT AVOIDANCE
    4.
    发明申请
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开
    内存单元表示避免

    公开(公告)号：WO2017222786A1

    公开(公告)日：2017-12-28

    申请号：PCT/US2017/035758

    申请日：2017-06-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： CALDERONI, Alessandro ,  RAMASWAMY, Durai Vishak Nirmal ,  PRALL, Kirk ,  BEDESCHI, Ferdinando

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described, A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

    Abstract translation: 描述了用于操作一个或多个铁电存储器单元的方法，系统和设备。单元可以被写入具有旨在传达与典型地与该值相关联的不同逻辑状态的值的值 。 例如，已经存储与一个逻辑状态相关的电荷一段时间的单元可以被重新写入以存储不同的电荷，并且重写的单​​元仍可以被读取以具有原始存储的逻辑状态。 指示器可被存储在锁存器中以指示当前由单元存储的逻辑状态是否是单元的预期逻辑状态。 例如，可以基于事件的发生或者基于确定小区已经存储了一个值（或电荷）达特定时间段，来周期性地重新写入小区。

    REDUCED PITCH LASER REDUNDANCY FUSE BANK STRUCTURE
    5.
    发明申请
    REDUCED PITCH LASER REDUNDANCY FUSE BANK STRUCTURE 审中-公开
    减少的激光雷达冗余保险丝银行结构

    公开(公告)号：WO1997023907A1

    公开(公告)日：1997-07-03

    申请号：PCT/US1996020300

    申请日：1996-12-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  PRALL, Kirk ,  STONE, Tod ,  ZAGAR, Paul, S.

    IPC: H01L23/525

    CPC classification number: G11C29/785 ,  G11C29/80 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses (101, 102, 103) of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

    Abstract translation: 公开了一种用于激光熔丝排的配置，其中可用空间被更有效地使用。 放置具有分级宽度和可变结构的熔丝（101,102,103），以使熔丝之间的平均距离最小化并使熔丝密度最大化。 或者，将公共源添加到标准激光熔丝结构中，使得其与保险丝相交，并且可用熔丝的数量加倍。

    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING
    7.
    发明公开
    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING 审中-公开
    具有不对称LOAD事件的详细状态存储器单元

    公开(公告)号：EP1719185A1

    公开(公告)日：2006-11-08

    申请号：EP05713587.3

    申请日：2005-02-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： PRALL, Kirk

    IPC: H01L29/792 ,  H01L29/788

    CPC classification number: H01L29/7887 ,  H01L29/7923

    Abstract: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide - nitride - oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide - nitride - oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

    MEMORY CELL IMPRINT AVOIDANCE
    9.
    发明公开
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开

    公开(公告)号：EP3926629A1

    公开(公告)日：2021-12-22

    申请号：EP21189181.7

    申请日：2017-06-02

    Applicant: Micron Technology, Inc.

    Inventor： CALDERONI, Alessandro ,  RAMASWAMY, Durai Vishak Nirmal ,  PRALL, Kirk ,  BEDESCHI, Ferdinando

    IPC: G11C11/22 ,  G11C7/10 ,  G11C29/52 ,  G06F11/10 ,  G11C7/04

    Abstract: Method and electronic memory device to avoid imprint in a ferroelectric memory, the electronic memory device, comprising:
    a memory cell;
    a latch coupled with the memory cell; and
    a sense component coupled with the memory cell and the latch, the sense component operable to:
    determine a first logic state stored on the memory cell;
    receive an indicator stored on the latch indicating whether the first logic state stored on the memory cell is an intended logic state; and
    output a second logic state different from the first logic state stored on the memory cell based at least in part on the indicator stored on the latch.

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