公开(公告)号：WO2015031547A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/053028

申请日：2014-08-28

Applicant: MICROSOFT CORPORATION

Inventor： STRAUSS, Karin ,  FOWERS, Jeremy

IPC: G06F9/50 ,  G06F17/16 ,  G06F15/80 ,  G06F12/08

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/5066 ,  G06F15/8053 ,  G06F2209/5017

Abstract: Various embodiments relating to performing multiple computations are provided. In one embodiment, a computing system includes an off-chip storage device configured to store a plurality of stream elements and associated tags and a computation device. The computation device includes an on-chip storage device configured to store a plurality of independently addressable resident elements, and a plurality of parallel processing units. Each parallel processing unit may be configured to receive one or more stream elements and associated tags from the off-chip storage device and select one or more resident elements from a subset of resident elements driven in parallel from the on-chip storage device. A selected resident element may be indicated by an associated tag as matching a stream element. Each parallel processing unit may be configured to perform one or more computations using the one or more stream elements and the one or more selected resident elements.

Abstract translation: 提供了与执行多次计算有关的各种实施例。 在一个实施例中，计算系统包括被配置为存储多个流元素和相关联的标签的片外存储设备和计算设备。 该计算装置包括：片上存储装置，被配置为存储多个可独立寻址的驻留单元，以及多个并行处理单元。 每个并行处理单元可以被配置为从芯片外存储设备接收一个或多个流元素和相关联的标签，并且从片上存储设备并行驱动的驻留元件的子集中选择一个或多个驻留元素。 选择的驻留单元可以由相关联的标签指示为匹配流元素。 每个并行处理单元可以被配置为使用一个或多个流元素和一个或多个选择的驻留元素来执行一个或多个计算。

公开(公告)号：WO2015031700A2

公开(公告)日：2015-03-05

申请号：PCT/US2014/053316

申请日：2014-08-29

Applicant: MICROSOFT CORPORATION

Inventor： STRAUSS, Karin ,  FOWERS, Jeremy ,  OVTCHAROV, Kalin

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Various embodiments relating to encoding a sparse matrix into a data structure format that may be efficiently processed via parallel processing of a computing system are provided. In one embodiment, a sparse matrix may be received. A set of designated rows of the sparse matrix may be traversed until all non-zero elements in the sparse matrix have been placed in a first array. Each time a row in the set is traversed, a next non-zero element in that row may be placed in the first array. If all non-zero elements for a given row of the set of designated rows have been placed in the first array, the given row may be replaced in the set of designated rows with a next unprocessed row of the sparse matrix. The data structure in which the sparse matrix is encoded may be outputted. The data structure may include the first array.

Abstract translation: 提供了关于将稀疏矩阵编码成可以通过计算系统的并行处理而被有效地处理的数据结构格式的各种实施例。 在一个实施例中，可以接收稀疏矩阵。 可以遍历稀疏矩阵的一组指定行，直到稀疏矩阵中的所有非零元素已经被放置在第一阵列中。 每次遍历集合中的一行时，该行中的下一个非零元素可以放置在第一个数组中。 如果指定行集合中给定行的所有非零元素都已放置在第一个数组中，则可以在指定行集合中替换给定行，并使用稀疏矩阵的下一个未处理行。 可以输出其中编码稀疏矩阵的数据结构。 数据结构可以包括第一阵列。

公开(公告)号：WO2015013153A2

公开(公告)日：2015-01-29

申请号：PCT/US2014/047345

申请日：2014-07-21

Applicant: MICROSOFT CORPORATION

Inventor： DAVIS, John D. ,  STRAUSS, Karin ,  MANASSE, Mark Steven ,  GOPALAN, Parikshit S. ,  YEKHANIN, Sergey

IPC: G11C29/44

CPC classification number: G11C29/4401 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0064 ,  G11C16/3404 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/52 ,  G11C2029/0409

Abstract: A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.

Abstract translation: 存储器区域可读写时可以持续自我识别为故障。 可以使用替换编码技术将分配给故障存储器区域的信息分配给存储器中的该大小区域中的另一个。 对于相变存储器，可以提供至少两个故障状态用于持久地自我识别故障存储器区域; 一个状态处于最高电阻范围，另一个状态处于最低电阻范围。 当存在自我识别的存储器故障时，替换单元可用于移位或分配数据。 单独或组合的存储器控​​制器和存储器模块可以管理替换单元使用，并且如果故障单元尚未处于故障状态，则有助于将新发现的故障单元驱动到故障状态。

公开(公告)号：WO2013126244A1

公开(公告)日：2013-08-29

申请号：PCT/US2013/025794

申请日：2013-02-13

Applicant: MICROSOFT CORPORATION

Inventor： LYMBEROPOULOS, Dimitrios ,  RIVA, Oriana ,  STRAUSS, Karin

IPC: G06F17/00 ,  G06F11/30

CPC classification number: G06F17/30902

Abstract: The subject disclosure is directed towards a technology that timely pre-fetches content to a computing device based upon a prediction that a user will be requesting access to the content. Features comprising temporal features, spatial features, spatiotemporal features and/or other features associated with content are provided to a model trained at least in part with historical access data. The model returns information from which a determination of whether to pre-fetch the content is made.

Abstract translation: 主题公开涉及一种基于用户将要求访问内容的预测，及时地将内容预取到计算设备的技术。 将包括时间特征，空间特征，时空特征和/或与内容相关联的其他特征的特征提供给至少部分地用历史访问数据训练的模型。 该模型返回是否进行预取内容的确定的信息。

公开(公告)号：WO2014081860A2

公开(公告)日：2014-05-30

申请号：PCT/US2013/071063

申请日：2013-11-20

Applicant: MICROSOFT CORPORATION

Inventor： STRAUSS, Karin ,  SAMPSON, Adrian ,  CEZE, Luis Henrique

CPC classification number: G06F9/46 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1666 ,  G06F17/10

Abstract: A system and method are provided for enhancing approximate computing by a computer system. In one example, an interface is provided comprising a variable-identifier module and a bit-priority module. The variable-identifier module is configured to identify one or more variables of data that are to be processed by the computer system with approximate precision. Approximate precision is a precision level at which a hardware device does not guarantee full data-correctness for the one or more variables. The bit-priority module is configured to assign bit-priorities to the one or more variables. The bit-priorities include relative levels of importance among bits of each of the one or more variables. The relative levels of importance include at least high-priority bits and low-priority bits.

Abstract translation: 提供了一种用于通过计算机系统增强近似计算的系统和方法。 在一个示例中，提供了包括可变标识符模块和比特优先级模块的接口。 可变识别器模块被配置为以近似的精度识别要由计算机系统处理的数据的一个或多个变量。 近似精度是硬件设备不能保证一个或多个变量具有完全数据正确性的精度级别。 位优先级模块被配置为将位优先级分配给一个或多个变量。 位优先级包括一个或多个变量中的每一个的位的重要性的相对级别。 相对重要性级别至少包括高优先级位和低优先级位。

公开(公告)号：WO2014078695A1

公开(公告)日：2014-05-22

申请号：PCT/US2013/070365

申请日：2013-11-15

Applicant: MICROSOFT CORPORATION

Inventor： STRAUSS, Karin ,  SMITH, Burton J. ,  MCKINLEY, Kathryn S.

IPC: G06F12/02 ,  G11C16/34 ,  G11C29/02

CPC classification number: G06F12/0246 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/0409

Abstract: The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage.

Abstract translation: 本文讨论的技术标识存储器区域中的存储器的故障段。 然后，技术可以通过使用重映射处理在存储器区域的外围部分逻辑地聚类存储器的故障段来管理存储器的故障段。 重新映射过程可以包括创建和存储为存储器区域定义段重映射条目的重映射元数据。 因此，故障聚类逻辑地消除或减少了内存碎片，使得系统可以为对象存储分配较大部分的连续存储器。

公开(公告)号：WO2014164032A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/020056

申请日：2014-03-04

Applicant: MICROSOFT CORPORATION

Inventor： STRAUSS, Karin ,  SAMPSON, Adrian ,  CEZE, Luis Henrique ,  BURGER, Douglas C.

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/06

CPC classification number: G11C27/005 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/06 ,  G11C16/3495

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract translation: 本技术放宽了MLC存储器等存储器操作（例如写入或读取）的精度（或全数据正确性 - 保证）要求，使得应用可以将数字数据值写入和读取为近似值。 MLC的类型包括闪存MLC和MLC相变存储器（PCM）以及其他电阻技术。 许多软件应用程序可能不需要通常用于存储和读取数据值的精度或精度。 例如，应用可以在相对低分辨率的显示器上呈现图像，并且可能不需要每个像素的精确数据值。 通过放松精度或正确性要求是存储器操作，MLC存储器可以具有增加的性能，寿命，密度和/或能量效率。

公开(公告)号：WO2012109631A2

公开(公告)日：2012-08-16

申请号：PCT/US2012/024776

申请日：2012-02-11

Applicant: MICROSOFT CORPORATION

Inventor： BLACK, Richard John ,  HARRIS, Timothy ,  MCILROY, Ross Cameron ,  STRAUSS, Karin

IPC: G06F15/80 ,  G06F15/167 ,  G06F13/14

CPC classification number: G06F15/167 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0866

Abstract: A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.

Abstract translation: 描述了具有共享物理存储器的多核处理器。 在一个实施例中，发送核心发送存储器写入请求到目的地核心，使得该请求可以由目的地核心作用，就好像它源自目的地核心一样。 在一个示例中，数据结构被配置在共享物理存储器中并被映射为可被发送核心和目标核心访问。 在一个示例中，共享数据结构被用作发送核心和目标核心之间的消息通道，以使用存储器写入请求来携带数据。 在一个实施例中，使用共享物理存储器启用通知机制，以便通过更新通知数据结构来通知事件的目标核心。 在一个例子中，通知机制触发目标核心的通知过程，以通知接收过程通知。

公开(公告)号：EP2673717A2

公开(公告)日：2013-12-18

申请号：EP12744863.7

申请日：2012-02-11

Applicant: Microsoft Corporation

Inventor： BLACK, Richard John ,  HARRIS, Timothy ,  MCILROY, Ross Cameron ,  STRAUSS, Karin

IPC: G06F15/80 ,  G06F15/167 ,  G06F13/14

CPC classification number: G06F15/167 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0866

Abstract: A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.

公开(公告)号：EP2817731A1

公开(公告)日：2014-12-31

申请号：EP13751191.1

申请日：2013-02-13

Applicant: Microsoft Corporation

Inventor： LYMBEROPOULOS, Dimitrios ,  RIVA, Oriana ,  STRAUSS, Karin

IPC: G06F17/00 ,  G06F11/30

CPC classification number: G06F17/30902

Abstract: The subject disclosure is directed towards a technology that timely pre-fetches content to a computing device based upon a prediction that a user will be requesting access to the content. Features comprising temporal features, spatial features, spatiotemporal features and/or other features associated with content are provided to a model trained at least in part with historical access data. The model returns information from which a determination of whether to pre-fetch the content is made.