公开(公告)号：MY153036A

公开(公告)日：2014-12-31

申请号：MYPI2010000816

申请日：2010-02-24

Applicant: MIMOS BERHAD

Inventor： YUSOFF YUZMAN ,  MAJID HASMAYADI ABDUL ,  YEW TAN KONG ,  SULAIMAN MOHD SHAHIMAN ,  MUSA ROHANA ,  RAZALI NABIHAH ,  SON WEE LEONG ,  BAHARIM ROZAIMAH ,  LAH HANIF CHE ,  OTHMAN NAZALIZA ,  WAHAB ROHAYA ABDUL ,  SALEH SHARIFAH

IPC: H03M1/12

Abstract: THE PRESENT INVENTION RELATES TO AN ANALOG TO DIGITAL CONVERTER (ADC) 100. THE ADC 100 IS COMPRISED OF A QUANTIZER COMPONENT 10 FOR SAMPLING AN INCOMING ANALOG SIGNAL AND GENERATING A DIGITAL SIGNAL; A RESIDUE GENERATOR COMPONENT 20 FOR SAMPLING THE INCOMING ANALOG SIGNAL AND FOR GENERATING A DIGITAL SIGNAL, AND A RESIDUE GENERATOR COMPONENT 20 FOR SAMPLING THE INCOMING ANALOG SIGNAL AND FOR GENERATING A RESIDUAL ANALOG SIGNAL WITH RESPECT TO THE DIGITAL SIGNAL. THE QUANTIZER COMPONENT 10 IS OF A DYNAMIC TYPE WHEREIN NO PREAMPLIFIER IS USED THEREIN AND IS SWITCHABLY CONNECTED TO A SOURCE 110 OF INCOMING ANALOG SIGNALS. THE QUANTIZER COMPONENT 10 IS COMPRISED OF A COMPARATOR CIRCUIT 30 HAVING A PLURALITY OF FIRST TRANSISTORS FOR SUBSTANTIALLY ACTING AS VOLTAGE-CONTROLLED RESISTORS THEREIN, AND A PLURALITY OF SECOND TRANSISTORS FOR SUBSTANTIALLY FORMING A LATCH THEREIN. THE RESIDUE GENERATOR 20 IS SWITCHABLY CONNECTED TO THE SOURCE 110 OF THE INCOMING ANALOG SIGNALS. THE INPUT OF THE RESIDUE GENERATOR COMPONENT IS CONNECTED TO THE OUTPUT OF THE QUANTIZER COMPONENT. THE COMPARATOR CIRCUIT 30 AND THE SWITCHABLE CONNECTION ARE FOR MATCHING THE SAMPLING CHARACTERISTICS OF THE QUANTIZER AND THE RESIDUE GENERATOR COMPONENTS 10 & 20. THE MOST ILLUSTRATIVE DRAWING:

公开(公告)号：MY156473A

公开(公告)日：2016-02-26

申请号：MYUI20094151

申请日：2009-10-05

Applicant: MIMOS BERHAD

Inventor： YUSOFF YUZMAN ,  LAH HANIF CHE ,  YEW TAN KONG ,  SULAIMAN MOHD SHAHIMAN ,  MUSA ROHANA ,  SON WEE LEONG ,  RAZALI NABIHAH ,  OTHMAN NAZALIZA ,  BAHARIM ROZAIMAH ,  MAJID HASMAYADI ABDUL ,  WAHAB ROHAYA ABDUL ,  SALEH SHARIFAH

IPC: H03M1/12

Abstract: A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:

公开(公告)号：WO2009070001A3

公开(公告)日：2009-10-15

申请号：PCT/MY2009000012

申请日：2009-01-13

Applicant: MIMOS BERHAD ,  WEE LEONG SON ,  YUSOFF YUZMAN ,  BAHARIM ROZAIMAH

Inventor： WEE LEONG SON ,  YUSOFF YUZMAN ,  BAHARIM ROZAIMAH

IPC: H03M1/38 ,  H03M1/36

CPC classification number: H03M1/0604 ,  H03M1/46 ,  H03M1/765

Abstract: For a SAR ADC with having an integrated programmable voltage reference function, a process for the voltage programmable positive voltage reference integrated to SAR ADC, includes; a) integrating a bandgap (21) to provides a stable voltage b) scaling up to a higher voltage by first Opamp (22) from the bandgap (21) and the voltage divided by the first resistor string (24) and second resistor string (25) to provides taps for the different voltage levels c) buffering the voltage at second Opamp (23) d) transferring the voltage to the decoding network (28) e) decoding the voltage by the decoder having at least one signal (29) and connecting the voltage to at least one resistor string (27) and at least one resistor string (27) tap point to the input third Opamp (30) f) buffering the voltage at the third Opamp (30) and the output becoming voltage reference programmable g) used as voltage reference at the digital-to-analog DAC (12) and the output of the converted voltage becoming voltage digital-to-analog (Vdac) h) sending the Vdac to the comparator (13) and the output of the comparator sending to the SAR (11) i) modifying the Vdac contents bit by bit until the data are the digital equivalent of the analog input j) repeating steps (a) through (i) until a predetermined number of trials have been completed.

Abstract translation: 对于具有集成可编程电压参考功能的SAR ADC，集成到SAR ADC的电压可编程正电压参考的过程包括： a）集成带隙（21）以提供稳定的电压b）通过第一Opamp（22）从带隙（21）和由第一电阻器串（24）和第二电阻器串（...）分压的电压来扩展到更高的电压 提供用于不同电压电平的抽头c）缓冲第二运算放大器（23）处的电压d）将电压传送到解码网络（28）e）解码器具有至少一个信号（29）和 将电压连接到至少一个电阻器串（27）和至少一个电阻器串（27）分接点到输入的第三运算放大器（30）f）缓冲第三运算放大器（30）处的电压，并且输出变为电压基准可编程 g）用作数模转换器DAC（12）上的参考电压，并将转换后的电压的输出变为电压数模（Vdac），h）将Vdac发送到比较器（13），并输出 比较器发送到SAR（11）i）逐位修改Vdac内容，直到数据为止 模拟输入的数字等价物j）重复步骤（a）至（i），直到预定数量的试验完成。