公开(公告)号：MY153036A

公开(公告)日：2014-12-31

申请号：MYPI2010000816

申请日：2010-02-24

Applicant: MIMOS BERHAD

Inventor： YUSOFF YUZMAN ,  MAJID HASMAYADI ABDUL ,  YEW TAN KONG ,  SULAIMAN MOHD SHAHIMAN ,  MUSA ROHANA ,  RAZALI NABIHAH ,  SON WEE LEONG ,  BAHARIM ROZAIMAH ,  LAH HANIF CHE ,  OTHMAN NAZALIZA ,  WAHAB ROHAYA ABDUL ,  SALEH SHARIFAH

IPC: H03M1/12

Abstract: THE PRESENT INVENTION RELATES TO AN ANALOG TO DIGITAL CONVERTER (ADC) 100. THE ADC 100 IS COMPRISED OF A QUANTIZER COMPONENT 10 FOR SAMPLING AN INCOMING ANALOG SIGNAL AND GENERATING A DIGITAL SIGNAL; A RESIDUE GENERATOR COMPONENT 20 FOR SAMPLING THE INCOMING ANALOG SIGNAL AND FOR GENERATING A DIGITAL SIGNAL, AND A RESIDUE GENERATOR COMPONENT 20 FOR SAMPLING THE INCOMING ANALOG SIGNAL AND FOR GENERATING A RESIDUAL ANALOG SIGNAL WITH RESPECT TO THE DIGITAL SIGNAL. THE QUANTIZER COMPONENT 10 IS OF A DYNAMIC TYPE WHEREIN NO PREAMPLIFIER IS USED THEREIN AND IS SWITCHABLY CONNECTED TO A SOURCE 110 OF INCOMING ANALOG SIGNALS. THE QUANTIZER COMPONENT 10 IS COMPRISED OF A COMPARATOR CIRCUIT 30 HAVING A PLURALITY OF FIRST TRANSISTORS FOR SUBSTANTIALLY ACTING AS VOLTAGE-CONTROLLED RESISTORS THEREIN, AND A PLURALITY OF SECOND TRANSISTORS FOR SUBSTANTIALLY FORMING A LATCH THEREIN. THE RESIDUE GENERATOR 20 IS SWITCHABLY CONNECTED TO THE SOURCE 110 OF THE INCOMING ANALOG SIGNALS. THE INPUT OF THE RESIDUE GENERATOR COMPONENT IS CONNECTED TO THE OUTPUT OF THE QUANTIZER COMPONENT. THE COMPARATOR CIRCUIT 30 AND THE SWITCHABLE CONNECTION ARE FOR MATCHING THE SAMPLING CHARACTERISTICS OF THE QUANTIZER AND THE RESIDUE GENERATOR COMPONENTS 10 & 20. THE MOST ILLUSTRATIVE DRAWING:

公开(公告)号：MY156473A

公开(公告)日：2016-02-26

申请号：MYUI20094151

申请日：2009-10-05

Applicant: MIMOS BERHAD

Inventor： YUSOFF YUZMAN ,  LAH HANIF CHE ,  YEW TAN KONG ,  SULAIMAN MOHD SHAHIMAN ,  MUSA ROHANA ,  SON WEE LEONG ,  RAZALI NABIHAH ,  OTHMAN NAZALIZA ,  BAHARIM ROZAIMAH ,  MAJID HASMAYADI ABDUL ,  WAHAB ROHAYA ABDUL ,  SALEH SHARIFAH

IPC: H03M1/12

Abstract: A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:

公开(公告)号：MY158579A

公开(公告)日：2016-10-14

申请号：MYPI2011700103

申请日：2011-07-07

Applicant: MIMOS BERHAD

Inventor： YEW TAN KONG ,  YEE NG MEI

IPC: H03M1/00

Abstract: The present invention relates to a method for converting analog signal to digital signal using a successive approximation register analog to digital converter. The method allows the SAR-ADC (100) to go through a first iteration of bit cycling and then stores the most significant bits and monitor bits in a register of the SAR-ADC (100). The most significant bits are fixed for the subsequent iteration of bit cycling until a change has been detected to the monitor bits. The most illustrative drawing:

公开(公告)号：MY149749A

公开(公告)日：2013-10-14

申请号：MYPI2010006018

申请日：2010-12-16

Applicant: MIMOS BERHAD

Inventor： YEW TAN KONG

IPC: H03M1/12

Abstract: A DUAL-FUNCTION ANALOG TO DIGITAL CONVERTER IS DISCLOSED COMPRISING AN ANALOG FRONT END (104), A FUNCTIONALITY SELECTION CIRCUITRY, A DIGITAL TO ANALOG CONVERTER (102), A COMPARATOR (106), A SUCCESSIVE APPROXIMATION REGISTER LOGIC (112) AND AN OUTPUT REGISTER (114). THE ANALOG FRONT END (104) COUPLES AN INPUT SIGNAL TO THE COMPARATOR (106) FOR EITHER ANALOG TO DIGITAL CONVERSION OR CAPACITANCE TO DIGITAL CONVERSION. THE FUNCTIONALITY SELECTION CIRCUITRY DETERMINES THE INPUT SIGNAL COUPLED TO THE COMPARATOR (106) AS BEING EITHER AN OUTPUT OF THE DIGITAL TO ANALOG CONVERTER (102) OR AN ANALOG INPUT CAPACITANCE SIGNAL. THE DIGITAL TO ANALOG CONVERTER (102) GENERATES A SCALED REFERENCE VOLTAGE REQUIRED BY THE COMPARATOR (106). THE COMPARATOR (106) COMPARES THE INPUT SIGNAL AND THE SCALED REFERENCE VOLTAGE TO GENERATE A COMPARISON RESULT. THE SUCCESSIVE APPROXIMATION REGISTER LOGIC PERFORMS SUCCESSIVE APPROXIMATION BASED ON THE COMPARISON RESULT FROM THE COMPARATOR (106) TO GENERATE EITHER A SCALED OUTPUT REQUIRED BY THE DIGITAL TO ANALOG CONVERTER (102) OR A DIGITAL OUTPUT PROPORTIONAL TO THE INPUT SIGNAL STORED IN THE OUTPUT REGISTER (114).