Abstract:
A sensor for measuring semiconductor wafer temperature in semiconductor processing equipment, comprising a first laser to provide a first laser beam at a first wavelength and a second laser to provide a second laser beam at a second wavelength. The sensor also includes laser driver and oscillator to modulate the wavelength of the first and second laser beams as the laser beams are directed to and reflected from the wafer, and detector module to measure the change in specular reflectance of the wafer resulting from the modulation of the wavelength of the first and second laser beams. The sensor system also includes signal processing circuitry to determine rms surface roughness of wafer at a known reference temperature from the change in reflectance of wafer resulting from modulation of the wavelengths of the first and second laser beams, and to determine the temperature of wafer from the change in specular reflectance of wafer resulting from modulation of the wavelengths of the first and second laser beams while wafer is at an unknown temperature and the surface roughness of the wafer at the known temperature.
Abstract:
A sensor (100) for measuring semiconductor wafer (10) temperature in semiconductor processing equipment (30), comprising a first laser (104) to provide a first laser beam at a first wavelength and a second laser (106) to provide a second laser beam at a second wavelength. The sensor also includes laser driver (108) and oscillator (110) to modulate the wavelength of the first and second laser beams as the laser beams are directed to and reflected from the wafer (10), and detector module (130) to measure the change in specular reflectance of the wafer (10) resulting from the modulation of the wavelength of the first and second laser beams. The sensor system also includes signal processing circuitry (138) to determine rms surface roughness of wafer (10) at a known reference temperature from the change in reflectance of wafer (10) resulting from modulation of the wavelengths of the first and second laser beams, and to determine the temperature of wafer (10) from the change in specular reflectance of wafer (10) resulting from modulation of the wavelengths of the first and second laser beams while wafer (10) is at an unknown temperature and the surface roughness of the wafer at the known temperature.
Abstract:
Back contact back junction three dimensional solar cell and methods for manufacturing are provided. The back contact back contact back junction three dimensional solar cell comprises a three-dimensional substrate. The substrate comprises a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer is positioned on the doped backside emitter region. Backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of three-dimensional solar cell.
Abstract:
Methods and systems for manufacturing thin-film solar cells utilizing a template having inverted pyramidal cavities defined by a plurality of walls aligned along a (111) crystallographic orientation plane and methods for manufacturing the template. Methods and systems for manufacturing thin-film solar cells utilizing a 3-D TFSS having a plurality of ridges on the surface of the semiconductor substrate defining a base opening of an inverted pyramidal cavity and walls defining an inverted pyramidal cavity and methods for manufacturing the 3-D TFSS. A 3-D TFSC comprising a semiconductor substrate with an inverted pyramidal cavity, emitter metallization regions on ridges on the surface of the semiconductor substrate which define an opening of the inverted pyramidal cavity, and base metallization regions on a region which form the apex of the inverted pyramidal cavity and methods for manufacturing the 3-D TFSC.
Abstract:
A back contact solar cell structure having a light receiving frontside and a metallized backside of on-cell patterned base and emitter metallization electrically connected to base and emitter regions on a back contact solar cell semiconductor substrate. A backplane laminate layer made of resin and fibers and having a coefficient of thermal expansion relatively matched to the back contact solar cell semiconductor substrate is attached to the on-cell base and emitter metallization and to portions of the back contact solar cell semiconductor substrate not covered by the on-cell base and emitter metallization.
Abstract:
Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.
Abstract:
A back contact back junction thin-film solar cell is formed on a thin-film semiconductor solar cell. Preferably the thin film semiconductor material comprises crystalline silicon. Emitter regions, selective emitter regions, and a back surface field are formed through ion implantation and annealing processes.
Abstract:
High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.
Abstract:
In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode regions separated by a frontside trench through the top semiconductor layer at least to an underlying insulating layer positioned between the top semiconductor layer and a bottom semiconductor layer. A dielectric layer covers the top exposed surfaces of the carrier. Backside trenches through the bottom semiconductor layer at least to the insulating layer form isolated backside regions corresponding to the frontside positive and negative electrode regions. Backside contacts positioned on the bottom semiconductor layer and coupled to the positive and negative electrode regions allow for the electric charging of the frontside electrode regions.