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    Method and equipment for recovering sign clock from signal having wide frequency possibility
    1.
    发明专利
    Method and equipment for recovering sign clock from signal having wide frequency possibility 审中-公开
    从具有广泛的可能性的信号恢复标志时钟的方法和设备

    公开(公告)号：JP2005167295A

    公开(公告)日：2005-06-23

    申请号：JP2002115369

    申请日：2002-04-17

    Applicant: Motorola Inc ,  モトローラ・インコーポレイテッドMotorola Incorporated

    Inventor： KULL A CORBETT S ,  BAKKE BRADLEY B ,  ARENS JOHN W

    IPC: H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/027 ,  H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227

    CPC classification number: H04L7/007 ,  H04L27/2273

    Abstract: PROBLEM TO BE SOLVED: To provide a device for recovering a code clock from a received signal having wide frequency errors or offsets. SOLUTION: Intensity values of received sampling in-phase and quadrature phase signals are determined (210). The intensity values are summed and distributed (227) in accumulator registers 231, 233, 235, 237 and 239, and the sum of first and second signals is totalized over respective sampling times and substantially predicted burst lengths. A maximum/minimum value determination circuit 240 selects a sampling time having a maximum or minimum sum and provides a recovered clock signal 270. Then a carrier is recovered (260), and a down sampler 250 down-samples the received in-phase and quadrature phase signals based on the recovered clock signal. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于从具有宽频率误差或偏移的接收信号中恢复码时钟的装置。 解决方案：确定接收采样同相和正交相位信号的强度值（210）。 强度值在累加器寄存器231,233,235,237和239中相加和分布（227），并且第一和第二信号的和在相应的采样时间和基本上预测的突发长度上被合计。 最大/最小值确定电路240选择具有最大或最小和的并且提供恢复的时钟信号270的采样时间。然后恢复载波（260），下采样器250对接收到的同相和正交 基于恢复的时钟信号的相位信号。 版权所有（C）2005，JPO＆NCIPI

    METODO Y APARATO DE COMUNICACION DIGITAL DE DECISION BLANDA.
    2.
    发明专利
    METODO Y APARATO DE COMUNICACION DIGITAL DE DECISION BLANDA. 未知

    公开(公告)号：ES2113300A1

    公开(公告)日：1998-04-16

    申请号：ES9502093

    申请日：1995-10-27

    Applicant: MOTOROLA INC

    Inventor： BLASIAK DARIUSZ A ,  ARENS JOHN W

    IPC: H04L27/22 ,  H03D3/06 ,  H03D3/22 ,  H03K20060101 ,  H03M13/00 ,  H03M13/23 ,  H04L20060101 ,  H04L1/00 ,  H04L27/227 ,  H04Q7/20

    Abstract: Método y aparato de comunicación digital de decisión blanda. El aparato decodificador (200) decodifica una señal coherente modulada por modulación digital de fase multinivel codificada diferencialmente (DEPSK). Un receptor coherente (101) recibe y, ulteriormente, entrega la señal coherente modulada por DEPSK a un computador métrico (201). El computador métrico (201) genera una métrica de decisión blanda {A ({s (n)) correspondiente a la señal coherente modulada por DEPSK que se entrega a un decodificador de corrección de errores hacia delante (FEC) (107). El decodificador de FEC (107) decodifica la señal coherente modulada por DEPSK según la métrica de decisión blanda {A ({s (n)) correspondiente a la señal coherente modulada por DEPSK.

    8.
    发明专利
    未知

    公开(公告)号：BR9105733A

    公开(公告)日：1992-05-19

    申请号：BR9105733

    申请日：1991-04-09

    Applicant: MOTOROLA INC

    Inventor： ARENS JOHN W ,  BORTH DAVID E ,  KEPLER JAMES F

    IPC: H04B1/16 ,  H03G3/20 ,  H04B1/30 ,  H04B7/005 ,  H04L27/14 ,  H04L27/22

    Abstract: There is provided a mechanism for Automatic Gain Control in a receiver. It comprises: determining, within a certain dynamic range, the difference in power between the desired signal and a signal received, and providing open loop gain control for the signal in response to the differential so determined, scaled by the receiver's gain characteristics, such that the signal is positioned within dynamic range so as to reduce saturation and noise.

    9.
    发明专利
    未知

    公开(公告)号：FR2734107B1

    公开(公告)日：2002-11-29

    申请号：FR9605535

    申请日：1996-05-03

    Applicant: MOTOROLA INC

    Inventor： KULL A CORBETT S ,  BAKKE BRADLEY B ,  ARENS JOHN W

    IPC: H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/027 ,  H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04B7/212 ,  H04L12/43

    Abstract: The present invention provides an apparatus for symbol clock recovery from a received signal having wide range of frequency errors or offsets. Magnitudes of received inphase and quadrature sampled signals are determined (210). These magnitudes are summed and distributed (227) into accumulator registers (231, 232, 233, 235, 237, 239) for accumulating sums of the first and second signals for each sample time and substantially over a length of an expected burst. A maximum-minimum determination circuit (240) chooses the sample time having a largest or smallest sum to provide a recovered clock signal (270). The carrier could then be recovered (260), and a downsampler (250) downsamples the received inphase and quadrature signals based on the recovered clock signal.

    10.
    发明专利
    未知

    公开(公告)号：FR2734107A1

    公开(公告)日：1996-11-15

    申请号：FR9605535

    申请日：1996-05-03

    Applicant: MOTOROLA INC

    Inventor： KULL A CORBETT S ,  BAKKE BRADLEY B ,  ARENS JOHN W

    IPC: H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/027 ,  H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04B7/212 ,  H04L12/43

    Abstract: The present invention provides an apparatus for symbol clock recovery from a received signal having wide range of frequency errors or offsets. Magnitudes of received inphase and quadrature sampled signals are determined (210). These magnitudes are summed and distributed (227) into accumulator registers (231, 232, 233, 235, 237, 239) for accumulating sums of the first and second signals for each sample time and substantially over a length of an expected burst. A maximum-minimum determination circuit (240) chooses the sample time having a largest or smallest sum to provide a recovered clock signal (270). The carrier could then be recovered (260), and a downsampler (250) downsamples the received inphase and quadrature signals based on the recovered clock signal.

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